static int gen6_do_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
int ret;
/* Hold gt_lock across reset to prevent any register access
* with forcewake not set correctly
*/
mtx_lock(&dev_priv->gt_lock);
/* Reset the chip */
/* GEN6_GDRST is not in the gt power well, no need to check
* for fifo space for the write or forcewake the chip for
* the read
*/
I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
/* Spin waiting for the device to ack the reset request */
ret = _intel_wait_for(dev,
(I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
500, 0, "915rst");
/* If reset with a user forcewake, try to restore, otherwise turn it off */
if (dev_priv->forcewake_count)
dev_priv->display.force_wake_get(dev_priv);
else
dev_priv->display.force_wake_put(dev_priv);
/* Restore fifo count */
dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
mtx_unlock(&dev_priv->gt_lock);
return (ret);
}
static int
intel_gmbus_transfer(device_t idev, struct iic_msg *msgs, uint32_t nmsgs)
{
struct intel_iic_softc *sc;
struct drm_i915_private *dev_priv;
u8 *buf;
int error, i, reg_offset, unit;
u32 val, loop;
u16 len;
sc = device_get_softc(idev);
dev_priv = sc->drm_dev->dev_private;
unit = device_get_unit(idev);
sx_xlock(&dev_priv->gmbus_sx);
if (sc->force_bit_dev) {
error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs);
goto out;
}
reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
I915_WRITE(GMBUS0 + reg_offset, sc->reg0);
for (i = 0; i < nmsgs; i++) {
len = msgs[i].len;
buf = msgs[i].buf;
if ((msgs[i].flags & IIC_M_RD) != 0) {
I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT |
(i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) |
(len << GMBUS_BYTE_COUNT_SHIFT) |
(msgs[i].slave << GMBUS_SLAVE_ADDR_SHIFT) |
GMBUS_SLAVE_READ | GMBUS_SW_RDY);
POSTING_READ(GMBUS2 + reg_offset);
do {
loop = 0;
if (_intel_wait_for(sc->drm_dev,
(I915_READ(GMBUS2 + reg_offset) &
(GMBUS_SATOER | GMBUS_HW_RDY)) != 0,
50, 1, "915gbr"))
goto timeout;
if ((I915_READ(GMBUS2 + reg_offset) &
GMBUS_SATOER) != 0)
goto clear_err;
val = I915_READ(GMBUS3 + reg_offset);
do {
*buf++ = val & 0xff;
val >>= 8;
} while (--len != 0 && ++loop < 4);
} while (len != 0);
} else {
static int
ironlake_do_reset(struct drm_device *dev, u8 flags)
{
struct drm_i915_private *dev_priv;
u32 gdrst;
dev_priv = dev->dev_private;
gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
return (_intel_wait_for(dev,
(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1) != 0,
500, 1, "915rst"));
}
static int
i965_do_reset(struct drm_device *dev, u8 flags)
{
u8 gdrst;
/*
* Set the domains we want to reset (GRDOM/bits 2 and 3) as
* well as the reset bit (GR/bit 0). Setting the GR bit
* triggers the reset; when done, the hardware will clear it.
*/
gdrst = pci_read_config(dev->device, I965_GDRST, 1);
pci_write_config(dev->device, I965_GDRST, gdrst | flags | 0x1, 1);
return (_intel_wait_for(dev, i965_reset_complete(dev), 500, 1,
"915rst"));
}
