void sb_last_sata_cache(void)
{
u32 base;
u32 val;
pcitag_t sata_dev = _pci_make_tag(0, 0x12, 0);
PRINTF_DEBUG();
if(ati_sb_cfg.sata_cache_base){
/* store sata base, size and signature */
base = ati_sb_cfg.sata_cache_base | 0xa0000000;
*(volatile u32 *)(base + 0x08) = ati_sb_cfg.sata_cache_base;
*(volatile u32 *)(base + 0x04) = ati_sb_cfg.sata_cache_size;
*(volatile u8 *)(base + 0x00) = 'A';
*(volatile u8 *)(base + 0x01) = 'T';
*(volatile u8 *)(base + 0x02) = 'i';
*(volatile u8 *)(base + 0x03) = 'B';
/* disable IO access */
set_sbcfg_enable_bits(sata_dev, 0x04, 1 << 0, 0 << 0);
/* reserved bit */
set_sbcfg_enable_bits(sata_dev, 0x40, 1 << 20, 1 << 20);
/* set cache base addr */
val = _pci_conf_read(sata_dev, 0x10);
val &= 0x00ffffff;
val |= (ati_sb_cfg.sata_cache_base >> 24) << 24;
_pci_conf_write(sata_dev, 0x10, val);
}
void sb_last_c3_popup_setting(void)
{
pcitag_t dev;
u32 base, reg10;
u8 type = get_sb600_platform();
PRINTF_DEBUG();
if(type == K8_ID){
dev = _pci_make_tag(0, 20, 5);
reg10 = _pci_conf_read(dev, 0x10);
if( (reg10 != 0xffffffff) && (reg10 != 0x00) ){
/* RPR8.3 K8 C3Pop-up for AC97, AC97_Memory_Mapped 0x80[1] = 1.
* If the CPU is K8, and C3PopUp function is enabled, then the BIOS should
* set this mirror bit to inform the ac97 driver that C3Pop-up is enabled.
* The driver will in turn not set the SetBusBusy bit in Memory_Mapped 0x04[14]
*/
base = (reg10 & 0xfffffff0) | 0xA0000000;
*(volatile u8 *)(base + 0x80) |= 1 << 1;
}
}else{
/* RPR2.4.2 C-State Function for the P4 platform
* Intel cpu C3 setting
* Smbus_PCI_config 0x64 [5] = 0 BmReq# is no longer used in P4 platform. Clear this bit
* to disable the BmReq# input.
* Smbus_PCI_config 0x64 [4] = 1
*/
dev = _pci_make_tag(0, 20, 0);
set_sbcfg_enable_bits(dev, 0x64, 1 << 5, 0 << 5);
set_sbcfg_enable_bits(dev, 0x64, 1 << 4, 1 << 4);
}
return;
}
/***************************************
* Legacy devices are mapped to LPC space.
* serial port 0
* KBC Port
* ACPI Micro-controller port
* LPC ROM size,
* NOTE: Call me ASAP, because I will reset LPC ROM size!
* NOTE : by general, it is called after HT emulation
***************************************/
void sb600_lpc_init(void)
{
u8 reg8;
u32 reg32;
pcitag_t sm_dev = _pci_make_tag(0, 20, 0);
pcitag_t lpc_dev = _pci_make_tag(0, 20, 3);
/* Enable lpc controller */
reg32 = _pci_conf_read(sm_dev, 0x64);
reg32 |= 0x00100000;
_pci_conf_write(sm_dev, 0x64, reg32);
/* Serial 0 : 0x3f8~0x3ff */
reg8 = _pci_conf_readn(lpc_dev, 0x44, 1);
reg8 |= (1 << 6);
_pci_conf_writen(lpc_dev, 0x44, reg8, 1);
/* PS/2 keyboard, ACPI : 0x60/0x64 & 0x62/0x66 */
reg8 = _pci_conf_readn(lpc_dev, 0x47, 1);
reg8 |= (1 << 5) | (1 << 6);
_pci_conf_writen(lpc_dev, 0x47, reg8, 1);
/* SuperIO, LPC ROM */
reg8 = _pci_conf_readn(lpc_dev, 0x48, 1);
reg8 |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */
reg8 |= (1 << 3) | (1 << 4); /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */
reg8 |= 1 << 6; /* enable for RTC I/O range */
_pci_conf_writen(lpc_dev, 0x48, reg8, 1);
/* hardware should enable LPC ROM by pin strapes */
/* rom access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */
/* See detail in BDG-215SB600-03.pdf page 15. */
_pci_conf_writen(lpc_dev, 0x68, 0x000e, 2); /* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB; */
_pci_conf_writen(lpc_dev, 0x6c, 0xfff0, 2); /* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB */
}
void atiSbirqSmi(void)
{
u32 base, temp;
pcitag_t sm_dev = _pci_make_tag(0, 20, 0);;
base = _pci_conf_read(sm_dev, 0x74) & 0xffffffe0;
base |= 0xa0000000;
*(volatile u32 *)base = 0x10;
temp = *(volatile u32 *)(base + 0x10);
if (temp & 0x100) { // entry0 enable ?
*(volatile u32 *)base = 0x14;
temp = *(volatile u32 *)(base + 0x14);
if (temp & 0x100) { // entryr2 enable ?
*(volatile u32 *)base = 0x20;
temp = *(volatile u32 *)(base + 0x20);
if (temp & 0x100) { // entryr8 enable ?
/*flip-flop PIC interrupt maskbits */
u8 reg21;
reg21 = linux_inb(0x21);
linux_outb(reg21 | 1, 0x21);
linux_outb(reg21, 0x21);
return ;
}
}
}
set_pm_enable_bits(0x03, 1, 0);
return ;
}
int pci_read_config_dword(struct pci_device *linuxpd, int reg, u32 *val)
{
if ((reg & 3) || reg < 0 || reg >= 0x100) {
printf ("pci_read_config_dword: bad reg %x\n", reg);
return -1;
}
*val=_pci_conf_read(linuxpd->pa.pa_tag, reg);
return 0;
}
/*
* nb_lock :
* close or hide unsed modules and lock the whole NB registers
*/
static void nb_lock(void)
{
pcitag_t nb_dev = _pci_make_tag(0, 0, 0);
pcitag_t igfx_dev = _pci_make_tag(1, 5, 0);
u32 base;
u32 val;
/* enable 2D optimization as configured */
if(ati_nb_cfg.gfx_config & (GFX_SP_ENABLE | GFX_UMA_ENABLE)){
if( (!(ati_nb_cfg.ext_config & EXT_DEBUG_GFX32BIT_MODE)) && (ati_nb_cfg.gfx_config & GFX_2D_OPTIMIZATION) ){
base = (_pci_conf_read(igfx_dev, 0x18) & 0xfffffff0) | 0xA0000000;
if(base){
/* open memory access */
set_nbcfg_enable_bits(igfx_dev, 0x04, 1 << 1, 1 << 1);
/* enable 2D accelerator */
val = *(volatile u32 *)(base | 0x4100); // 0x40FC + 4 ???
val |= 1 << 0;
*(volatile u32 *)(base | 0x4100) = val;
DEBUG_INFO("NB POST STAGE : nb_lock : 2D enable : address abnormal?\n");
}
}
}
/* enable decode for debug BAR */
if( (ati_nb_cfg.gfx_config & (GFX_SP_ENABLE | GFX_UMA_ENABLE)) && (_pci_conf_read(nb_dev, 0x8C) & (1 << 9)) ){
set_nbcfg_enable_bits(nb_dev, 0x8C, 1 << 10, 1 << 10);
}else{
set_nbcfg_enable_bits(nb_dev, 0x8C, 3 << 9, 0 << 9);
}
/* Hide PM2 bar */
set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 17, 0 << 17);
/* set proper unused index for inderect space */
/* lock the NB */
set_nbmisc_enable_bits(nb_dev, 0x00, (1 << 0) | (1 << 7), (1 << 0) | (1 << 7));
return;
}
/* Get SB ASIC Revision.*/
u8 get_sb600_revision(void)
{
pcitag_t sb_dev = _pci_make_tag(0, 0x14, 0);
u8 rev;
u32 reg32;
rev = _pci_conf_readn(sb_dev, 0x08, 1);
if(rev >= REV_SB600_A13){
reg32 = _pci_conf_read(sb_dev, 0x70);
reg32 |= 1 << 8;
_pci_conf_write(sb_dev, 0x70, reg32);
rev = _pci_conf_readn(sb_dev, 0x08, 1);
reg32 &= ~(1 << 8);
_pci_conf_write(sb_dev, 0x70, reg32);
}
return rev;
}
void sb600_lpc_port80(void)
{
u8 byte;
u32 dev;
u32 reg32;
/* enable lpc controller */
dev = _pci_make_tag(0, 20, 0);
reg32 = _pci_conf_read(dev, 0x64);
reg32 |= 0x00100000; /* lpcEnable */
_pci_conf_write(dev, 0x64, reg32);
/* enable prot80 LPC decode in pci function 3 configuration space. */
dev = _pci_make_tag(0, 20, 3);
byte = _pci_conf_readn(dev, 0x4a, 1);
byte |= 1 << 5; /* enable port 80 */
_pci_conf_writen(dev, 0x4a, byte, 1);
}
int sb700_acpi_init(void)
{
unsigned int temp32;
int loop;
unsigned int PM_IO_BASE;
device_t acpi_tag;
acpi_tag = _pci_make_tag(0, 20, 0);
PM_IO_BASE = _pci_conf_read(acpi_tag, 0x9c);
/* pm1 base */
pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xff);
pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
/* gpm base */
pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
/* gpm base */
pm_iowrite(0x2e, ACPI_END & 0xFF);
pm_iowrite(0x2f, ACPI_END >> 8);
/* io decode */
pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
* the contents of the PM registers at
* index 20-2B to decode ACPI I/O address.
* AcpiSmiEn & SmiCmdEn
*/
/* SLP_SMI_EN */
pmio_enable_bits(0x04,0x1<<7,0x00);
/* SlpS3ToLdtPwrGdEn */
pmio_enable_bits(0x41,0x1<<3,0x1<<3);
/* LongSlpS3 */
pmio_enable_bits(0x8d,0x1<<5,0x1<<5);
/* SCI_EN set P225 */
OUTW(1, ACPI_PM1_CNT_BLK);
OUTW(5<<10,ACPI_PM1_CNT_BLK);
OUTW(1<<13,ACPI_PM1_CNT_BLK);
}
void sb_last_sata_unconnected_shutdown_clock(void)
{
u8 sata_class = ati_sb_cfg.sata_class;
pcitag_t sata_dev = _pci_make_tag(0, 18, 0);
u32 temp;
PRINTF_DEBUG();
if(ati_sb_cfg.sata_ck_au_off == SB_ENABLE){ // auto off
if(ati_sb_cfg.sata_channel > 0){ // enable sata
switch(sata_class){
case 0 :
case 3 :
case 4 :
temp = _pci_conf_read(sata_dev, 0x40);
temp |= (ati_sb_cfg.sb600_sata_sts & 0xFF0F) << 16;
_pci_conf_write(sata_dev, 0x40, temp);
default :
}
}
}
return;
}
static void
_pci_query_dev_func (struct pci_device *dev, pcitag_t tag, int initialise)
{
pcireg_t id, class;
pcireg_t old, mask;
pcireg_t stat;
pcireg_t bparam;
int reg;
struct pci_bus *pb;
struct pci_device *pd;
unsigned int x;
int bus, device, function;
class = _pci_conf_read(tag, PCI_CLASS_REG);
id = _pci_conf_read(tag, PCI_ID_REG);
if (_pciverbose) {
int supported;
char devinfo[256];
_pci_devinfo(id, class, &supported, devinfo);
_pci_tagprintf (tag, "%s\n", devinfo);
}
pd = pmalloc(sizeof(struct pci_device));
if(pd == NULL) {
PRINTF ("pci: can't alloc memory for device\n");
return;
}
_pci_break_tag (tag, &bus, &device, &function);
/*
* sb_sata_init :
* sb sata init, for real device init and make it available
*/
void sb_sata_init(void)
{
pcitag_t sm_dev = _pci_make_tag(0, 20, 0);
pcitag_t ide_dev = _pci_make_tag(0, 20, 1);
pcitag_t sata_dev = _pci_make_tag(0, 18, 0);
u32 port_phy;
u8 port_bist;
u32 reg04;
u32 sata_bar5;
u8 rev, class;
/* enable the sata controller according to config */
if(ati_sb_cfg.sata_smbus == SB_ENABLE){
// enable
set_sbcfg_enable_bits(sm_dev, 0xAD, 1 << 1, 0 << 1);
}else{
// disable
set_sbcfg_enable_bits(sm_dev, 0xAD, 1 << 1, 1 << 1);
}
/* enable proper SATA channel based on config : '0' none, '1' SATA1 */
if(ati_sb_cfg.sata_channel == SB_DISABLE){
// disable SATA1
set_sbcfg_enable_bits(sm_dev, 0xAD, 1 << 0, 0 << 0);
}else{
// enable SATA1 & set power saving mode
set_sbcfg_enable_bits(sm_dev, 0xAD, (1 << 0) | (1 << 5), (1 << 0) | (1 << 5));
}
/* BIT4 : disable fast boot
* BIT0 : enable write subsystem id
*/
set_sbcfg_enable_bits(sata_dev, 0x40, (1 << 0) | (1 << 4), (1 << 0) | (1 << 4));
/* disable SATA MSI cap */
set_sbcfg_enable_bits(sata_dev, 0x40, 1 << 23, 1 << 23);
/* disable IDP cap */
if(rev <= REV_SB600_A21){
set_sbcfg_enable_bits(sata_dev, 0x40, 1 << 25, 1 << 25);
}
/* setting device class */
class = ati_sb_cfg.sata_class;
if(class == 3){
/* IDE native mode setting */
set_sbcfg_enable_bits(ide_dev, 0x08, 0xFF << 8, 0x8F << 8);
}
/* SATA class mode setting */
_pci_conf_write(sata_dev, 0x08, sata_class_table[class]);
/* disable SATA class write */
set_sbcfg_enable_bits(sata_dev, 0x40, 1 << 0, 0 << 0);
/* program wdt with 16 retries before timer timeout */
set_sbcfg_enable_bits(sata_dev, 0x44, 0xff << 16, 0x10 << 16);
if(rev == REV_SB600_A11){
/* PHY global tuning x86 to 0x2400 */
_pci_conf_writen(sata_dev, 0x86, 0x2400, 2);
/* PHY tuning for ports */
port_phy = 0x00B420D8;
port_bist = 0x00;
}else{
/* PHY global tuning x86 to 0x2400 */
_pci_conf_writen(sata_dev, 0x86, 0x2c00, 2);
if(rev == REV_SB600_A12){
port_phy = 0x00B4005A;
port_bist = 0xB8;
}else if(rev == REV_SB600_A13){
port_phy = 0x00B401DA;
port_bist = 0xB8;
if(ati_sb_cfg.sata_phy_avdd == SB_ENABLE){ // phy AVDD is 1.25V
port_phy = 0x00B401D5;
port_bist = 0x78;
}
}else{
port_phy = 0x00B401D6;
port_bist = 0xB8;
}
}
/* tuning 4 ports phy */
_pci_conf_write(sata_dev, 0x88, port_phy);
_pci_conf_write(sata_dev, 0x8C, port_phy);
_pci_conf_write(sata_dev, 0x90, port_phy);
_pci_conf_write(sata_dev, 0x94, port_phy);
_pci_conf_writen(sata_dev, 0xA5, port_bist, 1);
_pci_conf_writen(sata_dev, 0xAD, port_bist, 1);
_pci_conf_writen(sata_dev, 0xB5, port_bist, 1);
_pci_conf_writen(sata_dev, 0xBD, port_bist, 1);
/* port reset */
delay(1000); // delay 1ms
/* get sata bar5 base address */
reg04 = _pci_conf_read(sata_dev, 0x04);
if( (_pci_conf_read(sata_dev, 0x24) & 0xfffffff0) == 0 ){
_pci_conf_write(sata_dev, 0x24, TEMP_SATA_BAR5_BASE);
sata_bar5 = TEMP_SATA_BAR5_BASE | 0xA0000000;
}else{
sata_bar5 = (_pci_conf_read(sata_dev, 0x24) & 0xfffffff0) | 0xA0000000;
}
/* enable io/mem access */
set_sbcfg_enable_bits(sata_dev, 0x04, (1 << 0) | (1 << 1), (1 << 0) | (1 << 1));
/* RPR 6.10 Hide Support-Aggressive-Link-Power-Management Capability
* in AHCI HBA Capabilities Register (For all SB600)
* 1. SATA_PCI_config 0x40 [0] = 1
* Unlocks configuration register so that HBA AHCI Capabilities Register
* can be modified.
* 2. SATA_BAR5 + 0xFC [11] = 0
* (CFG_CAP_SALP Disabled) Clearing this bit has the following effects:
* Support-Aggressive-Link-Power-Management Capability is hidden from
* software in AHCI HBA Capabilities Register.
* As a result,;software will not enable the HBA to aggressively enter
* power-saving (Partial/Slumber) mode.
* 6.12 Hiding Slumber and Partial State Capabilities in AHCI HBA Capabilities
* Register
* 2. SATA_BAR5 + 0xFC [27] = 1 (CFG_CAP_SALP Disabled)
* 3. SATA_PCI_config 0x40 [0]= 0
* Clears the bit to lock configuration registers so that AHCI HBA
* Capabilities Register is read-only.
*/
set_sbcfg_enable_bits(sata_dev, 0x40, 1 << 0, 1 << 0);
*(volatile u32 *)(sata_bar5 + 0xFC) &= ~(1 << 11);
*(volatile u32 *)(sata_bar5 + 0xFC) |= 1 << 27;
if(ati_sb_cfg.sata_port_mult_cap != SB_ENABLE){
*(volatile u32 *)(sata_bar5 + 0xFC) &= ~(1 << 12);
}
if(rev >= REV_SB600_A21){
if(ati_sb_cfg.sata_hot_plug_cap != SB_ENABLE){
*(volatile u32 *)(sata_bar5 + 0xFC) &= ~(1 << 17);
}
}
set_sbcfg_enable_bits(sata_dev, 0x40, 1 << 0, 0 << 0);
/* RPR6.11 Disabling SATA Interface Partial/Slumber States Power Management
* Transitions (For all SB600 )
* Port0: SATA_BAR5 + 0x12C[11:08] = 0x03
* Port1: SATA_BAR5 + 0x1AC[11:08] = 0x03
* Port2: SATA_BAR5 + 0x22C[11:08] = 0x03
* Port3: SATA_BAR5 + 0x2AC[11:08] = 0x03
* Setting PxSCTL (Port X Serial ATA Control) register bits[11:8] (PxSCTL.IPM)
* to 0x03 will disable interface power management states,
* both Partial and Slumber. HBA is not allowed to initiate these two states,
* and HBA must PMNAK any request from device to enter these states.
*/
*(volatile u32 *)(sata_bar5 + 0x12C) |= 3 << 8;
*(volatile u32 *)(sata_bar5 + 0x1AC) |= 3 << 8;
*(volatile u32 *)(sata_bar5 + 0x22C) |= 3 << 8;
*(volatile u32 *)(sata_bar5 + 0x2AC) |= 3 << 8;
/* restore pci cmd */
_pci_conf_write(sata_dev, 0x04, reg04);
return;
}
/*
* sata_drive_detect :
* detect the sata drive and put it into proper config
*/
static void sata_drive_detecting(void)
{
int ports = 4, count;
int timeout;
u32 base, reg32, reg04;
u32 val;
pcitag_t sata_dev = _pci_make_tag(0, 18, 0);
PRINTF_DEBUG();
reg04 = _pci_conf_read(sata_dev, 0x04);
/* force memory and io enabled */
set_sbcfg_enable_bits(sata_dev, 0x04, 0x03 << 0, 0x03 << 0);
/* ahci base addr */
base = (_pci_conf_read(sata_dev, 0x24) & 0xfffffff0) | 0xA0000000;
DEBUG_INFO("ahci base addr is %x \n", base);
/* 4/PM 3/SM 2/PS 1/SS */
while(ports){
count = 3;
while(count){
/* judge is the phy and communication is ok */
delay(1000); // delay 1 ms
reg32 = *(volatile u32 *)(base + 0x128);
DEBUG_INFO("sata status : reg128 0x%x\n", reg32);
if((reg32 & 0x0000000F) == 0x03){
goto drive_is_stable;
}
/* test if bsy bit is set, it means the drive is connected */
reg32 = *(volatile u32 *)(base + 0x120);
if((reg32 & 0x80) == 0){
val = *(volatile u32 *)(base + 0x128);
if((val & 0x0f) != 0x1){
goto drive_is_stable;
}
}
count--;
}
/* now drive is not stable even after waitting for 1 sec,so downgrade to GEN 1 */
reg32 = *(volatile u32 *)(base + 0x12C);
if((reg32 & 0x0f) == 0x10){
goto drive_is_stable; // jump if already GEN1
}
/* store the sata status */
ati_sb_cfg.sb600_sata_sts |= (0x8 << ports);
/* set to GEN1 : reset the status*/
reg32 = *(volatile u32 *)(base + 0x12C);
reg32 = (reg32 & 0x0f) | 0x10;
*(volatile u32 *)(base + 0x12C) = reg32;
reg32 |= 0x01;
*(volatile u32 *)(base + 0x12C) = reg32; // force 00B
delay(1000); //wait 1 ms
reg32 = *(volatile u32 *)(base + 0x12C);
reg32 &= 0xfe;
*(volatile u32 *)(base + 0x12C) = reg32;
/* re detect the device again */
ports--;
continue;
drive_is_stable:
reg32 = *(volatile u32 *)(base + 0x128);
if ((reg32 & 0x0f) == 0x3){
u16 sata_bar;
sata_bar = _pci_conf_readn(sata_dev, 0x10, 2);
if(ports & 0x01){
sata_bar = _pci_conf_readn(sata_dev, 0x18, 2);
}
sata_bar &= ~(7);
sata_bar += 0x06;
if(ports <= 2){
val |= 0xA0;
}else{
val |= 0xB0;
}
linux_outb(val, sata_bar);
sata_bar++;
timeout = 3000;
while(timeout--){
val = linux_inb(sata_bar);
val &= 0x88000000;
if(val == 0x00){
break;
}
delay(10 * 1000);
}
/* update the status */
ati_sb_cfg.sb600_sata_sts ^= (1 << (4 - ports));
}
base += 0x80; // increase status offset by 80h for next port
--ports;
} /* while(i) */
/* restore PCI conf cmd */
_pci_conf_write(sata_dev, 0x04, reg04);
return;
}
/*
* nb_misc_clock :
* rs690 misc clock parameters setting
*/
static void nb_misc_clock(void)
{
pcitag_t clk_dev = _pci_make_tag(0, 0, 1);
pcitag_t nb_dev = _pci_make_tag(0, 0, 0);
pcitag_t gfx_dev2 = _pci_make_tag(0, 2, 0);
u8 rev = get_nb_revision();
u32 val;
/* visible CLK func */
set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 0, 1 << 0);
if(ati_nb_cfg.ext_config & EXT_DEBUG_NB_DYNAMIC_CLK){
/* disable NB dynamic clock to htiu rx */
set_nbcfg_enable_bits(clk_dev, 0xE8, 0x07 << 12, 1 << 13);
/* ENABLE : CLKGATE_DIS_GFX_TXCLK & CLKGATE_DIS_GPPSB_CCLK & CLKGATE_DIS_CFG_S1X */
set_nbcfg_enable_bits(clk_dev, 0x94, (1 << 16) | (1 << 24) | (1 << 28), 0);
/* ENABEL : CLKDATE_DIS_IOC_CCLK_MST/SLV, enabel clkdate for C/MCLK goto BIF branch */
set_nbcfg_enable_bits(clk_dev, 0x8C, (1 << 13) | (1 << 14) | (1 << 24) | (1 << 25), 0);
if(rev < REV_RS690_A21){
/* CKLGATE_DIS_IO_CCLK_MST */
set_nbcfg_enable_bits(clk_dev, 0x8C, 1 << 13, 1 << 13);
}
/* Powering Down efuse and strap block clocks in GFX mode as default */
set_nbcfg_enable_bits(clk_dev, 0xCC, 1 << 24, 1 << 24);
/* dynamic clock setting for MC and HTIU */
val = nbmc_read_index(nb_dev, 0x7A);
val &= 0xffffffc0;
val |= 1 << 2;
if(rev >= REV_RS690_A21){
val &= ~(1 << 6);
set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11);
}
nbmc_write_index(nb_dev, 0x7A, val);
if(ati_nb_cfg.gfx_config & (GFX_SP_ENABLE | GFX_UMA_ENABLE)){
/* Powering Down efuse and strap block clocks in GFX mode : PWM???*/
set_nbcfg_enable_bits(clk_dev, 0xCC, (1 << 23) | (1 << 24), 1 << 24);
}else{
/* nb only mode */
/* Powers down reference clock to graphics core PLL */
set_nbcfg_enable_bits(clk_dev, 0x8C, 1 << 21, 1 << 21);
/* Powering Down efuse and strap block clocks after boot-up */
set_nbcfg_enable_bits(clk_dev, 0xCC, (1 << 23) | (1 << 24), (1 << 23) | (1 << 24));
/* powerdown clock to MC */
set_nbcfg_enable_bits(clk_dev, 0xE4, 1 << 0, 1 << 0);
}
if(ati_nb_cfg.pcie_gfx_info == 0){
if(_pci_conf_read(gfx_dev2, 0x00) == 0xffffffff){
/* Powerdown GFX ports clock when no external GFX detected */
set_nbcfg_enable_bits(clk_dev, 0xE8, 1 << 17, 1 << 17);
}
}
}
/* hide CLK func */
set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 0, 0 << 0);
if(rev >= REV_RS690_A21){
set_htiu_enable_bits(nb_dev, 0x05, (1 << 8) | (1 << 9), (1 << 8) | (1 << 9));
set_htiu_enable_bits(nb_dev, 0x05, (1 << 10), (1 << 10));
}
DEBUG_INFO("NB POST STAGE : nb_misc_clock function : should we use PWM for efuse and strap powerdown?\n");
return;
}
