void
SH3dev::tmu_dump()
{
	uint8_t r8;

	DPRINTF((TEXT("<<<TMU>>>\n")));
	/* Common */
	/* TOCR  timer output control register */
	r8 = _reg_read_1(SH3_TOCR);
	DPRINTF((TEXT("TCLK = %S\n"),
	    r8 & SH3_TOCR_TCOE ? "RTC output" : "input"));
	/* TSTR */
	r8 = _reg_read_1(SH3_TSTR);
	DPRINTF((TEXT("Timer start(#0:2) [%c][%c][%c]\n"),
	    r8 & SH3_TSTR_STR0 ? 'x' : '_',
	    r8 & SH3_TSTR_STR1 ? 'x' : '_',
	    r8 & SH3_TSTR_STR2 ? 'x' : '_'));

#define	CHANNEL_DUMP(a, x)						\
	tmu_channel_dump(x, SH##a##_TCOR##x,				\
			 SH##a##_TCNT##x,				\
			 SH##a##_TCR##x##)
	CHANNEL_DUMP(3, 0);
	CHANNEL_DUMP(3, 1);
	CHANNEL_DUMP(3, 2);
#undef	CHANNEL_DUMP
	DPRINTF((TEXT("\n")));
}
Exemplo n.º 2
0
void
__smap_status(int msg)
{
	static int cnt;
	__gsfb_print(1, "%d: tx=%d rx=%d txcnt=%d free=%d cnt=%d\n", msg,
	    _reg_read_1(SMAP_TXFIFO_FRAME_REG8),
	    _reg_read_1(SMAP_RXFIFO_FRAME_REG8), __sc->tx_desc_cnt,
	    __sc->tx_buf_freesize, cnt++);
}
Exemplo n.º 3
0
int
smap_intr(void *arg)
{
	struct smap_softc *sc = arg;
	struct ifnet *ifp;
	u_int16_t cause, disable, r;

	cause = _reg_read_2(SPD_INTR_STATUS_REG16) &
	    _reg_read_2(SPD_INTR_ENABLE_REG16);

	disable = cause & (SPD_INTR_RXDNV | SPD_INTR_TXDNV);
	if (disable) {
		r = _reg_read_2(SPD_INTR_ENABLE_REG16);
		r &= ~disable;
		_reg_write_2(SPD_INTR_ENABLE_REG16, r);

		printf("%s: invalid descriptor. (%c%c)\n", DEVNAME,
		    disable & SPD_INTR_RXDNV ? 'R' : '_',
		    disable & SPD_INTR_TXDNV ? 'T' : '_');

		if (disable & SPD_INTR_RXDNV)
			smap_rxeof(arg);

		_reg_write_2(SPD_INTR_CLEAR_REG16, disable);
	}

	if (cause & SPD_INTR_TXEND) {
		_reg_write_2(SPD_INTR_CLEAR_REG16, SPD_INTR_TXEND);
		if (_reg_read_1(SMAP_RXFIFO_FRAME_REG8) > 0)
			cause |= SPD_INTR_RXEND;
		smap_txeof(arg);
	}

	if (cause & SPD_INTR_RXEND) {
		_reg_write_2(SPD_INTR_CLEAR_REG16, SPD_INTR_RXEND);
		smap_rxeof(arg);
		if (sc->tx_desc_cnt > 0 &&
		    sc->tx_desc_cnt > _reg_read_1(SMAP_TXFIFO_FRAME_REG8))
			smap_txeof(arg);
	}

	if (cause & SPD_INTR_EMAC3)
		emac3_intr(arg);
	
	/* if transmission is pending, start here */
	ifp = &sc->ethercom.ec_if;
	if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
		smap_start(ifp);
#if NRND > 0
	rnd_add_uint32(&sc->rnd_source, cause | sc->tx_fifo_ptr << 16);
#endif

	return (1);
}
Exemplo n.º 4
0
void
sh_rtc_set(void *cookie, struct clock_ymdhms *dt)
{
	uint8_t r;

	/* stop clock */
	r = _reg_read_1(SH_(RCR2));
	r |= SH_RCR2_RESET;
	r &= ~SH_RCR2_START;
	_reg_write_1(SH_(RCR2), r);

	/* set time */
	if (CPU_IS_SH3)
		_reg_write_1(SH3_RYRCNT, TOBCD(dt->dt_year % 100));
	else
		_reg_write_2(SH4_RYRCNT, TOBCD(dt->dt_year % 100));
#define	RTCSET(x, y)	_reg_write_1(SH_(R ## x ## CNT), TOBCD(dt->dt_ ## y))
	RTCSET(MON, mon);
	RTCSET(WK, wday);
	RTCSET(DAY, day);
	RTCSET(HR, hour);
	RTCSET(MIN, min);
	RTCSET(SEC, sec);
#undef RTCSET
	/* start clock */
	_reg_write_1(SH_(RCR2), r | SH_RCR2_START);
}
Exemplo n.º 5
0
int
power_intr(void *arg)
{
	extern int kbd_reset;
	int status;

	status = (int8_t)_reg_read_1(LANDISK_BTNSTAT);
	if (status == -1) {
		return (0);
	}

	status = ~status;
	if (status & BTN_POWER_BIT) {
#ifdef DEBUG
		printf("%s switched\n", sc->sc_dev.dv_xname);
		Debugger();
#endif
		_reg_write_1(LANDISK_PWRSW_INTCLR, 1);
		if (kbd_reset == 1) {
			kbd_reset = 0;
			psignal(initproc, SIGUSR1);
		}
		return (1);
	}
	return (0);
}
Exemplo n.º 6
0
void
psh3pwr_sleep(void *self)
{
	/* splhigh on entry */
	extern void pfckbd_poll_hitachi_power(void);

	uint8_t phdr;

	phdr = _reg_read_1(SH7709_PHDR);
	_reg_write_1(SH7709_PHDR, phdr & ~PSH3_GREEN_LED_ON);

	pfckbd_poll_hitachi_power();

	phdr = _reg_read_1(SH7709_PHDR);
	_reg_write_1(SH7709_PHDR, phdr | PSH3_GREEN_LED_ON);
}
void
SH3dev::icu_dump()
{

	super::icu_dump_priority(_ipr_table);
	icu_control();
	DPRINTF((TEXT("ICR0   0x%08x\n"), _reg_read_2(SH3_ICR0)));
	DPRINTF((TEXT("ICR1   0x%08x\n"), _reg_read_2(SH3_ICR1)));
	DPRINTF((TEXT("ICR2   0x%08x\n"), _reg_read_2(SH3_ICR2)));
	DPRINTF((TEXT("PINTER 0x%08x\n"), _reg_read_2(SH3_PINTER)));
	DPRINTF((TEXT("IPRA   0x%08x\n"), _reg_read_2(SH3_IPRA)));
	DPRINTF((TEXT("IPRB   0x%08x\n"), _reg_read_2(SH3_IPRB)));
	DPRINTF((TEXT("IPRC   0x%08x\n"), _reg_read_2(SH3_IPRC)));
	DPRINTF((TEXT("IPRD   0x%08x\n"), _reg_read_2(SH3_IPRD)));
	DPRINTF((TEXT("IPRE   0x%08x\n"), _reg_read_2(SH3_IPRE)));
	DPRINTF((TEXT("IRR0   0x%08x\n"), _reg_read_1(SH3_IRR0)));
	DPRINTF((TEXT("IRR1   0x%08x\n"), _reg_read_1(SH3_IRR1)));
	DPRINTF((TEXT("IRR2   0x%08x\n"), _reg_read_1(SH3_IRR2)));
}
Exemplo n.º 8
0
static int
psh3pwr_intr_plug_in(void *self)
{
	struct psh3pwr_softc *sc __attribute__((__unused__)) =
	    (struct psh3pwr_softc *)self;
	uint8_t irr0, scpdr;

	irr0 = _reg_read_1(SH7709_IRR0);
	if (!(irr0 & IRR0_IRQ1))
		return 0;
	_reg_write_1(SH7709_IRR0, irr0 & ~IRR0_IRQ1);

	/* XXXX: WindowsCE sets this bit. */
	scpdr = _reg_read_1(SH7709_SCPDR);
	_reg_write_1(SH7709_SCPDR, scpdr & ~PSH3PWR_PLUG_OUT);

	DPRINTF(("%s: plug in\n", device_xname(&sc->sc_dev)));

	return 1;
}
Exemplo n.º 9
0
static int
btn_intr(void *arg)
{
	struct btn_obio_softc *sc = (void *)arg;
	device_t self = sc->sc_dev;
	int status;
	int i;

	status = (int8_t)_reg_read_1(LANDISK_BTNSTAT);
	if (status == -1) {
		return (0);
	}

	status = ~status;
	if (status & BTN_ALL_BIT) {
		if (status & BTN_RESET_BIT) {
			if (sc->sc_mask & BTN_RESET_BIT) {
				extintr_disable(sc->sc_ih);
#if NPWRSW_OBIO > 0
				extintr_disable_by_num(LANDISK_INTR_PWRSW);
#endif
				sysmon_task_queue_sched(0,
				    btn_sysmon_pressed_event, sc);
				return (1);
			} else {
				aprint_normal_dev(self,
					"reset button pressed\n");
			}
		}

		for (i = 0; i < NBUTTON; i++) {
			uint8_t mask = btnlist[i].mask;
			int rv = 0;
			if (status & mask) {
				if (sc->sc_mask & mask) {
					sysmon_task_queue_sched(1,
					    btn_pressed_event,
					    &sc->sc_bev[btnlist[i].idx]);
				} else {
					aprint_normal_dev(self,
						"%s button pressed\n",
						btnlist[i].name);
				}
				rv = 1;
			}
			if (rv != 0) {
				extintr_disable(sc->sc_ih);
				callout_schedule(&sc->sc_guard_ch, BTN_TIMEOUT);
			}
		}
		return (1);
	}
	return (0);
}
Exemplo n.º 10
0
int
smap_fifo_reset(bus_addr_t a)
{
	int retry = 10000;

	_reg_write_1(a, SMAP_FIFO_RESET);

	while ((_reg_read_1(a) & SMAP_FIFO_RESET) && --retry > 0)
		;

	return (retry == 0);
}
Exemplo n.º 11
0
void
sh_rtc_get(void *cookie, time_t base, struct clock_ymdhms *dt)
{
	int retry = 8;

	/* disable carry interrupt */
	_reg_bclr_1(SH_(RCR1), SH_RCR1_CIE);

	do {
		uint8_t r = _reg_read_1(SH_(RCR1));
		r &= ~SH_RCR1_CF;
		r |= SH_RCR1_AF; /* don't clear alarm flag */
		_reg_write_1(SH_(RCR1), r);

		if (CPU_IS_SH3)
			dt->dt_year = FROMBCD(_reg_read_1(SH3_RYRCNT));
		else
			dt->dt_year = FROMBCD(_reg_read_2(SH4_RYRCNT) & 0x00ff);

		/* read counter */
#define	RTCGET(x, y)	dt->dt_ ## x = FROMBCD(_reg_read_1(SH_(R ## y ## CNT)))
		RTCGET(mon, MON);
		RTCGET(wday, WK);
		RTCGET(day, DAY);
		RTCGET(hour, HR);
		RTCGET(min, MIN);
		RTCGET(sec, SEC);
#undef RTCGET
	} while ((_reg_read_1(SH_(RCR1)) & SH_RCR1_CF) && --retry > 0);

	if (retry == 0) {
		printf("rtc_gettime: couldn't read RTC register.\n");
		memset(dt, 0, sizeof(*dt));
		return;
	}

	dt->dt_year = (dt->dt_year % 100) + 1900;
	if (dt->dt_year < 1970)
		dt->dt_year += 100;
}
Exemplo n.º 12
0
/*ARGSUSED*/
static int
scimci_card_detect(sdmmc_chipset_handle_t sch)
{
	uint8_t reg;
	int s;

	s = splserial();
	CSR_SET_2(SH7709_PGCR, PGCR_EJECT, 0);
	reg = _reg_read_1(SH7709_PGDR);
	splx(s);

	return !(reg & PGDR_EJECT);
}
Exemplo n.º 13
0
void
blink_led(void *whatever)
{
	static struct timeout blink_tmo;
	u_int8_t ledctrl;

	if (led_blink == 0) {
		_reg_write_1(LANDISK_LEDCTRL,
		    LED_POWER_CHANGE | LED_POWER_VALUE);
		return;
	}

	ledctrl = (u_int8_t)_reg_read_1(LANDISK_LEDCTRL) & LED_POWER_VALUE;
	ledctrl ^= (LED_POWER_CHANGE | LED_POWER_VALUE);
	_reg_write_1(LANDISK_LEDCTRL, ledctrl);

	timeout_set(&blink_tmo, blink_led, NULL);
	timeout_add(&blink_tmo,
	    ((averunnable.ldavg[0] + FSCALE) * hz) >> FSHIFT);
}
Exemplo n.º 14
0
void
SH3dev::pfc_dump()
{
	DPRINTF((TEXT("<<<Pin Function Controller>>>\n")));
	DPRINTF((TEXT("[control]\n")));
#define	DUMP_PFC_REG(x)							\
	DPRINTF((TEXT("P%SCR :"), #x));					\
	bitdisp(_reg_read_2(SH3_P##x##CR))
	DUMP_PFC_REG(A);
	DUMP_PFC_REG(B);
	DUMP_PFC_REG(C);
	DUMP_PFC_REG(D);
	DUMP_PFC_REG(E);
	DUMP_PFC_REG(F);
	DUMP_PFC_REG(G);
	DUMP_PFC_REG(H);
	DUMP_PFC_REG(J);
	DUMP_PFC_REG(K);
	DUMP_PFC_REG(L);
#undef DUMP_PFC_REG
	DPRINTF((TEXT("SCPCR :")));
	bitdisp(_reg_read_2(SH3_SCPCR));
	DPRINTF((TEXT("\n[data]\n")));
#define	DUMP_IOPORT_REG(x)						\
	DPRINTF((TEXT("P%SDR :"), #x));					\
	bitdisp(_reg_read_1(SH3_P##x##DR))
	DUMP_IOPORT_REG(A);
	DUMP_IOPORT_REG(B);
	DUMP_IOPORT_REG(C);
	DUMP_IOPORT_REG(D);
	DUMP_IOPORT_REG(E);
	DUMP_IOPORT_REG(F);
	DUMP_IOPORT_REG(G);
	DUMP_IOPORT_REG(H);
	DUMP_IOPORT_REG(J);
	DUMP_IOPORT_REG(K);
	DUMP_IOPORT_REG(L);
#undef DUMP_IOPORT_REG
	DPRINTF((TEXT("SCPDR :")));
	bitdisp(_reg_read_1(SH3_SCPDR));
}
Exemplo n.º 15
0
static void
psh3pwr_attach(device_t parent, device_t self, void *aux)
{
	extern void (*__sleep_func)(void *);
	extern void *__sleep_ctx;
	struct psh3pwr_softc *sc = device_private(self);
	uint8_t phdr;

	sc->sc_dev = self;

	/* arrange for hpcapm to call us when power status is requested */
	config_hook(CONFIG_HOOK_GET, CONFIG_HOOK_ACADAPTER,
	    CONFIG_HOOK_EXCLUSIVE, psh3pwr_apm_getpower_hook, sc);
	config_hook(CONFIG_HOOK_GET, CONFIG_HOOK_CHARGE,
	    CONFIG_HOOK_EXCLUSIVE, psh3pwr_apm_getpower_hook, sc);
	config_hook(CONFIG_HOOK_GET, CONFIG_HOOK_BATTERYVAL,
	    CONFIG_HOOK_EXCLUSIVE, psh3pwr_apm_getpower_hook, sc);

	/* regisiter sleep function to APM */
	__sleep_func = psh3pwr_sleep;
	__sleep_ctx = self;

	phdr = _reg_read_1(SH7709_PHDR);
	_reg_write_1(SH7709_PHDR, phdr | PSH3_GREEN_LED_ON);

	aprint_naive("\n");
	aprint_normal("\n");

	sc->sc_ih_pout = intc_intr_establish(SH7709_INTEVT2_IRQ0,
	    IST_EDGE, IPL_TTY, psh3pwr_intr_plug_out, sc);
	sc->sc_ih_pin = intc_intr_establish(SH7709_INTEVT2_IRQ1,
	    IST_EDGE, IPL_TTY, psh3pwr_intr_plug_in, sc);

	/* XXXX: WindowsCE sets this bit. */
	aprint_normal_dev(self, "plug status: %s\n",
	    psh3pwr_ac_is_off() ? "out" : "in");
}
Exemplo n.º 16
0
psh3pwr_ac_is_off(void)
{

	return _reg_read_1(SH7709_SCPDR) & PSH3PWR_PLUG_OUT;
}
Exemplo n.º 17
0
void
SH3dev::hd64461_dump(platid_t &platform)
{
	uint16_t r16;
	uint8_t r8;

#define	MATCH(p)						\
	platid_match(&platform, &platid_mask_MACH_##p)

	DPRINTF((TEXT("<<<HD64461>>>\n")));
	if (!MATCH(HP_LX) &&
	    !MATCH(HP_JORNADA_6XX) &&
	    !MATCH(HITACHI_PERSONA_HPW230JC)) {
		DPRINTF((TEXT("don't exist.")));
		return;
	}

#if 0
	DPRINTF((TEXT("frame buffer test start\n")));
	uint8_t *fb = reinterpret_cast<uint8_t *>(HD64461_FBBASE);

	for (int i = 0; i < 320 * 240 * 2 / 8; i++)
		*fb++ = 0xff;
	DPRINTF((TEXT("frame buffer test end\n")));
#endif
	// System
	DPRINTF((TEXT("STBCR (System Control Register)\n")));
	r16 = _reg_read_2(HD64461_SYSSTBCR_REG16);
	bitdisp(r16);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_SYSSTBCR_##m, #m)
	DBG_BIT_PRINT(r16, CKIO_STBY);
	DBG_BIT_PRINT(r16, SAFECKE_IST);
	DBG_BIT_PRINT(r16, SLCKE_IST);
	DBG_BIT_PRINT(r16, SAFECKE_OST);
	DBG_BIT_PRINT(r16, SLCKE_OST);
	DBG_BIT_PRINT(r16, SMIAST);
	DBG_BIT_PRINT(r16, SLCDST);
	DBG_BIT_PRINT(r16, SPC0ST);
	DBG_BIT_PRINT(r16, SPC1ST);
	DBG_BIT_PRINT(r16, SAFEST);
	DBG_BIT_PRINT(r16, STM0ST);
	DBG_BIT_PRINT(r16, STM1ST);
	DBG_BIT_PRINT(r16, SIRST);
	DBG_BIT_PRINT(r16, SURTSD);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("SYSCR (System Configuration Register)\n")));
	r16 = _reg_read_2(HD64461_SYSSYSCR_REG16);
	bitdisp(r16);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_SYSSYSCR_##m, #m)
	DBG_BIT_PRINT(r16, SCPU_BUS_IGAT);
	DBG_BIT_PRINT(r16, SPTA_IR);
	DBG_BIT_PRINT(r16, SPTA_TM);
	DBG_BIT_PRINT(r16, SPTB_UR);
	DBG_BIT_PRINT(r16, WAIT_CTL_SEL);
	DBG_BIT_PRINT(r16, SMODE1);
	DBG_BIT_PRINT(r16, SMODE0);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("SCPUCR (CPU Data Bus Control Register)\n")));
	r16 = _reg_read_2(HD64461_SYSSCPUCR_REG16);
	bitdisp(r16);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_SYSSCPUCR_##m, #m)
	DBG_BIT_PRINT(r16, SPDSTOF);
	DBG_BIT_PRINT(r16, SPDSTIG);
	DBG_BIT_PRINT(r16, SPCSTOF);
	DBG_BIT_PRINT(r16, SPCSTIG);
	DBG_BIT_PRINT(r16, SPBSTOF);
	DBG_BIT_PRINT(r16, SPBSTIG);
	DBG_BIT_PRINT(r16, SPASTOF);
	DBG_BIT_PRINT(r16, SPASTIG);
	DBG_BIT_PRINT(r16, SLCDSTIG);
	DBG_BIT_PRINT(r16, SCPU_CS56_EP);
	DBG_BIT_PRINT(r16, SCPU_CMD_EP);
	DBG_BIT_PRINT(r16, SCPU_ADDR_EP);
	DBG_BIT_PRINT(r16, SCPDPU);
	DBG_BIT_PRINT(r16, SCPU_A2319_EP);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("\n")));

	// INTC
	DPRINTF((TEXT("NIRR (Interrupt Request Register)\n")));
	r16 = _reg_read_2(HD64461_INTCNIRR_REG16);
	bitdisp(r16);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_INTCNIRR_##m, #m)
	DBG_BIT_PRINT(r16, PCC0R);
	DBG_BIT_PRINT(r16, PCC1R);
	DBG_BIT_PRINT(r16, AFER);
	DBG_BIT_PRINT(r16, GPIOR);
	DBG_BIT_PRINT(r16, TMU0R);
	DBG_BIT_PRINT(r16, TMU1R);
	DBG_BIT_PRINT(r16, IRDAR);
	DBG_BIT_PRINT(r16, UARTR);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("NIMR (Interrupt Mask Register)\n")));
	r16 = _reg_read_2(HD64461_INTCNIMR_REG16);
	bitdisp(r16);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_INTCNIMR_##m, #m)
	DBG_BIT_PRINT(r16, PCC0M);
	DBG_BIT_PRINT(r16, PCC1M);
	DBG_BIT_PRINT(r16, AFEM);
	DBG_BIT_PRINT(r16, GPIOM);
	DBG_BIT_PRINT(r16, TMU0M);
	DBG_BIT_PRINT(r16, TMU1M);
	DBG_BIT_PRINT(r16, IRDAM);
	DBG_BIT_PRINT(r16, UARTM);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("\n")));

	// PCMCIA
	// PCC0
	DPRINTF((TEXT("[PCC0 memory and I/O card (SH3 Area 6)]\n")));
	DPRINTF((TEXT("PCC0 Interface Status Register\n")));
	r8 = _reg_read_1(HD64461_PCC0ISR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC0ISR_##m, #m)
	DBG_BIT_PRINT(r8, P0READY);
	DBG_BIT_PRINT(r8, P0MWP);
	DBG_BIT_PRINT(r8, P0VS2);
	DBG_BIT_PRINT(r8, P0VS1);
	DBG_BIT_PRINT(r8, P0CD2);
	DBG_BIT_PRINT(r8, P0CD1);
	DBG_BIT_PRINT(r8, P0BVD2);
	DBG_BIT_PRINT(r8, P0BVD1);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC0 General Control Register\n")));
	r8 = _reg_read_1(HD64461_PCC0GCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC0GCR_##m, #m)
	DBG_BIT_PRINT(r8, P0DRVE);
	DBG_BIT_PRINT(r8, P0PCCR);
	DBG_BIT_PRINT(r8, P0PCCT);
	DBG_BIT_PRINT(r8, P0VCC0);
	DBG_BIT_PRINT(r8, P0MMOD);
	DBG_BIT_PRINT(r8, P0PA25);
	DBG_BIT_PRINT(r8, P0PA24);
	DBG_BIT_PRINT(r8, P0REG);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC0 Card Status Change Register\n")));
	r8 = _reg_read_1(HD64461_PCC0CSCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m)
	DBG_BIT_PRINT(r8, P0SCDI);
	DBG_BIT_PRINT(r8, P0IREQ);
	DBG_BIT_PRINT(r8, P0SC);
	DBG_BIT_PRINT(r8, P0CDC);
	DBG_BIT_PRINT(r8, P0RC);
	DBG_BIT_PRINT(r8, P0BW);
	DBG_BIT_PRINT(r8, P0BD);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC0 Card Status Change Interrupt Enable Register\n")));
	r8 = _reg_read_1(HD64461_PCC0CSCIER_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m)
	DBG_BIT_PRINT(r8, P0CRE);
	DBG_BIT_PRINT(r8, P0SCE);
	DBG_BIT_PRINT(r8, P0CDE);
	DBG_BIT_PRINT(r8, P0RE);
	DBG_BIT_PRINT(r8, P0BWE);
	DBG_BIT_PRINT(r8, P0BDE);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\ninterrupt type: ")));
	switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) {
	case HD64461_PCC0CSCIER_P0IREQE_NONE:
		DPRINTF((TEXT("none\n")));
		break;
	case HD64461_PCC0CSCIER_P0IREQE_LEVEL:
		DPRINTF((TEXT("level\n")));
		break;
	case HD64461_PCC0CSCIER_P0IREQE_FEDGE:
		DPRINTF((TEXT("falling edge\n")));
		break;
	case HD64461_PCC0CSCIER_P0IREQE_REDGE:
		DPRINTF((TEXT("rising edge\n")));
		break;
	}

	DPRINTF((TEXT("PCC0 Software Control Register\n")));
	r8 = _reg_read_1(HD64461_PCC0SCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC0SCR_##m, #m)
	DBG_BIT_PRINT(r8, P0VCC1);
	DBG_BIT_PRINT(r8, P0SWP);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	// PCC1
	DPRINTF((TEXT("[PCC1 memory card only (SH3 Area 5)]\n")));
	DPRINTF((TEXT("PCC1 Interface Status Register\n")));
	r8 = _reg_read_1(HD64461_PCC1ISR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC1ISR_##m, #m)
	DBG_BIT_PRINT(r8, P1READY);
	DBG_BIT_PRINT(r8, P1MWP);
	DBG_BIT_PRINT(r8, P1VS2);
	DBG_BIT_PRINT(r8, P1VS1);
	DBG_BIT_PRINT(r8, P1CD2);
	DBG_BIT_PRINT(r8, P1CD1);
	DBG_BIT_PRINT(r8, P1BVD2);
	DBG_BIT_PRINT(r8, P1BVD1);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC1 General Contorol Register\n")));
	r8 = _reg_read_1(HD64461_PCC1GCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC1GCR_##m, #m)
	DBG_BIT_PRINT(r8, P1DRVE);
	DBG_BIT_PRINT(r8, P1PCCR);
	DBG_BIT_PRINT(r8, P1VCC0);
	DBG_BIT_PRINT(r8, P1MMOD);
	DBG_BIT_PRINT(r8, P1PA25);
	DBG_BIT_PRINT(r8, P1PA24);
	DBG_BIT_PRINT(r8, P1REG);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC1 Card Status Change Register\n")));
	r8 = _reg_read_1(HD64461_PCC1CSCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m)
	DBG_BIT_PRINT(r8, P1SCDI);
	DBG_BIT_PRINT(r8, P1CDC);
	DBG_BIT_PRINT(r8, P1RC);
	DBG_BIT_PRINT(r8, P1BW);
	DBG_BIT_PRINT(r8, P1BD);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC1 Card Status Change Interrupt Enable Register\n")));
	r8 = _reg_read_1(HD64461_PCC1CSCIER_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m)
	DBG_BIT_PRINT(r8, P1CRE);
	DBG_BIT_PRINT(r8, P1CDE);
	DBG_BIT_PRINT(r8, P1RE);
	DBG_BIT_PRINT(r8, P1BWE);
	DBG_BIT_PRINT(r8, P1BDE);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC1 Software Control Register\n")));
	r8 = _reg_read_1(HD64461_PCC1SCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC1SCR_##m, #m)
	DBG_BIT_PRINT(r8, P1VCC1);
	DBG_BIT_PRINT(r8, P1SWP);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	// General Control
	DPRINTF((TEXT("[General Control]\n")));
	DPRINTF((TEXT("PCC0 Output pins Control Register\n")));
	r8 = _reg_read_1(HD64461_PCCP0OCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m)
	DBG_BIT_PRINT(r8, P0DEPLUP);
	DBG_BIT_PRINT(r8, P0AEPLUP);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC1 Output pins Control Register\n")));
	r8 = _reg_read_1(HD64461_PCCP1OCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m)
	DBG_BIT_PRINT(r8, P1RST8MA);
	DBG_BIT_PRINT(r8, P1RST4MA);
	DBG_BIT_PRINT(r8, P1RAS8MA);
	DBG_BIT_PRINT(r8, P1RAS4MA);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PC Card General Control Register\n")));
	r8 = _reg_read_1(HD64461_PCCPGCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCCPGCR_##m, #m)
	DBG_BIT_PRINT(r8, PSSDIR);
	DBG_BIT_PRINT(r8, PSSRDWR);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	// GPIO
#define	GPIO_DUMP(x)							\
	bitdisp(_reg_read_2(HD64461_GPA##x##R_REG16));			\
	bitdisp(_reg_read_2(HD64461_GPB##x##R_REG16));			\
	bitdisp(_reg_read_2(HD64461_GPC##x##R_REG16));			\
	bitdisp(_reg_read_2(HD64461_GPD##x##R_REG16))

	DPRINTF((TEXT("GPIO Port Control Register\n")));
	GPIO_DUMP(C);
	DPRINTF((TEXT("GPIO Port Data Register\n")));
	GPIO_DUMP(D);
	DPRINTF((TEXT("GPIO Port Interrupt Control Register\n")));
	GPIO_DUMP(IC);
	DPRINTF((TEXT("GPIO Port Interrupt Status  Register\n")));
	GPIO_DUMP(IS);
}