Exemplo n.º 1
0
/*
 * See header file for description.
 */
portBASE_TYPE ICACHE_FLASH_ATTR
xPortStartScheduler( void )
{
	//set pendsv and systemtick as lowest priority ISR.
	//pendsv setting
			/*******GPIO sdio_clk isr*********/
#if 0
    _xt_isr_attach(ETS_GPIO_INUM, GPIOIntrHdl, NULL);
    _xt_isr_unmask(1<<ETS_GPIO_INUM);
#else
			/*******software isr*********/
   	_xt_isr_attach(ETS_SOFT_INUM, SoftIsrHdl, NULL);
    _xt_isr_unmask(1<<ETS_SOFT_INUM);
#endif

    /* Initialize system tick timer interrupt and schedule the first tick. */
    _xt_tick_timer_init();

    os_printf("xPortStartScheduler\n");
    vTaskSwitchContext();

//    REG_SET_BIT(0x3ff2006c, BIT(4));
	/* Restore the context of the first task that is going to run. */

	XT_RTOS_INT_EXIT();

	/* Should not get here as the tasks are now running! */
	return pdTRUE;
}
Exemplo n.º 2
0
void user_init(void)
{
    uart_set_baud(0, 115200);

    /* configure GPIOs */
    gpio_enable(gpio_frc1, GPIO_OUTPUT);
    gpio_enable(gpio_frc2, GPIO_OUTPUT);
    gpio_write(gpio_frc1, 1);

    /* stop both timers and mask their interrupts as a precaution */
    timer_set_interrupts(FRC1, false);
    timer_set_run(FRC1, false);
    timer_set_interrupts(FRC2, false);
    timer_set_run(FRC2, false);

    /* set up ISRs */
    _xt_isr_attach(INUM_TIMER_FRC1, frc1_interrupt_handler);
    _xt_isr_attach(INUM_TIMER_FRC2, frc2_interrupt_handler);

    /* configure timer frequencies */
    timer_set_frequency(FRC1, freq_frc1);
    timer_set_frequency(FRC2, freq_frc2);

    /* unmask interrupts and start timers */
    timer_set_interrupts(FRC1, true);
    timer_set_run(FRC1, true);
    timer_set_interrupts(FRC2, true);
    timer_set_run(FRC2, true);

    gpio_write(gpio_frc1, 0);
}
Exemplo n.º 3
0
void ICACHE_FLASH_ATTR ir_remote_init(uint16 gpio_pin_num, bool invert_logic_level)
{
	_gpio_pin_num = gpio_pin_num;

	_logic_low = invert_logic_level;
	_logic_high = !_logic_low;
	_pwm_lvl = _logic_low;

	GPIO_ConfigTypeDef gpioCfg;
	gpioCfg.GPIO_Pin = BIT(_gpio_pin_num);
	gpioCfg.GPIO_Mode = GPIO_Mode_Output;
	gpioCfg.GPIO_Pullup = GPIO_PullUp_DIS;
	gpio_config(&gpioCfg);

	GPIO_OUTPUT_SET(_gpio_pin_num, _logic_low);

	portENTER_CRITICAL();
	_xt_isr_attach(ETS_FRC_TIMER1_INUM, pwm_tim1_intr_handler);
	TM1_EDGE_INT_ENABLE();
	_xt_isr_unmask((1 << ETS_FRC_TIMER1_INUM));

	CLEAR_PERI_REG_MASK(FRC1_INT_ADDRESS, FRC1_INT_CLR_MASK);
	WRITE_PERI_REG(FRC1_CTRL_ADDRESS, CLOCK_DIV_256 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
	WRITE_PERI_REG(FRC1_LOAD_ADDRESS, 0);
	portEXIT_CRITICAL();
}
Exemplo n.º 4
0
void delta_sigma_start(uint32_t period, uint32_t range, uint8_t pins[],
                       uint8_t n_pins)
{
  // Stop the timer during configuration
  timer_set_run(FRC1, false);

  g_n_pins = n_pins;
  for (uint8_t i = 0; i < n_pins; ++i)
  {
    g_pins[i].gpio_mask = BIT(pins[i]);
    g_pins[i].duty = 0;
    g_pins[i].acc = 0;
    gpio_enable(pins[i], GPIO_OUTPUT);
  }
  g_range = range;

  timer_set_interrupts(FRC1, false);
  timer_set_divider(FRC1, TIMER_CLKDIV_256);
  if (period > TIMER_FRC1_MAX_LOAD)
  {
    printf("delta_sigma: period %u too large\n", period);
    period = TIMER_FRC1_MAX_LOAD;
  }
  timer_set_load(FRC1, period);
  timer_set_reload(FRC1, true);
  _xt_isr_attach(INUM_TIMER_FRC1, timer_isr, NULL);
  timer_set_interrupts(FRC1, true);
  timer_set_run(FRC1, true);
}
Exemplo n.º 5
0
void gpio_set_interrupt(const uint8_t gpio_num, const gpio_inttype_t int_type, gpio_interrupt_handler_t handler)
{
    gpio_interrupt_handlers[gpio_num] = handler;

    GPIO.CONF[gpio_num] = SET_FIELD(GPIO.CONF[gpio_num], GPIO_CONF_INTTYPE, int_type);
    if (int_type != GPIO_INTTYPE_NONE) {
        _xt_isr_attach(INUM_GPIO, gpio_interrupt_handler, NULL);
        _xt_isr_unmask(1<<INUM_GPIO);
    }
}
Exemplo n.º 6
0
void uart_set_custom_callback(uart_process_char_t cb) {
  s_custom_callback = cb;

#ifndef RTOS_SDK
  ETS_UART_INTR_ATTACH(rx_isr, 0);
  ETS_INTR_ENABLE(ETS_UART_INUM);
#else
  _xt_isr_attach(ETS_UART_INUM, rx_isr, 0);
  _xt_isr_unmask(1 << ETS_UART_INUM);
#endif
}
Exemplo n.º 7
0
bool mgos_uart_hal_init(struct mgos_uart_state *us) {
  /* Start with ints disabled. */
  WRITE_PERI_REG(UART_INT_ENA(us->uart_no), 0);
#ifdef RTOS_SDK
  _xt_isr_mask(1 << ETS_UART_INUM);
  _xt_isr_attach(ETS_UART_INUM, (void *) esp_uart_isr, NULL);
#else
  ETS_INTR_DISABLE(ETS_UART_INUM);
  ETS_UART_INTR_ATTACH(esp_uart_isr, NULL);
#endif
  return true;
}
Exemplo n.º 8
0
/*
 * Initialise the uart receiver
 */
void ICACHE_FLASH_ATTR
uart_rx_init(void)
{ 
	uart_rx_queue = xQueueCreate( 
		UART_RX_QUEUE_SIZE,
		sizeof(char)
	);
	uart_rx_overruns=0;
	uart_rx_bytes=0;
	/* _xt_isr_mask seems to cause Exception 20 ? */
	//_xt_isr_mask(1<<ETS_UART_INUM);
	_xt_isr_attach(ETS_UART_INUM, uart_isr, (void*)0);
	_xt_isr_unmask(1<<ETS_UART_INUM);
}
Exemplo n.º 9
0
void user_init(void)
{
    sdk_uart_div_modify(0, UART_CLK_FREQ / 115200);
    xTaskCreate(timerRegTask, (signed char *)"timerRegTask", 1024, NULL, 2, NULL);

    TIMER(0).CTRL = VAL2FIELD(TIMER_CTRL_CLKDIV, TIMER_CLKDIV_256) | TIMER_CTRL_RELOAD;
    TIMER(0).LOAD = 0x200000;

    TIMER(1).LOAD = VAL2FIELD(TIMER_CTRL_CLKDIV, TIMER_CLKDIV_256);

    DPORT.INT_ENABLE |= DPORT_INT_ENABLE_TIMER0 | DPORT_INT_ENABLE_TIMER1;
    _xt_isr_attach(INUM_TIMER_FRC1, frc1_handler);
    _xt_isr_unmask(1<<INUM_TIMER_FRC1);
    _xt_isr_attach(INUM_TIMER_FRC2, frc2_handler);
    _xt_isr_unmask(1<<INUM_TIMER_FRC2);

    TIMER(0).CTRL |= TIMER_CTRL_RUN;
    TIMER(1).CTRL |= TIMER_CTRL_RUN;

    dump_timer_regs("timer regs during user_init");
    dump_timer_regs("#2 timer regs during user_init");
    dump_timer_regs("#3 timer regs during user_init");
}
Exemplo n.º 10
0
void user_init(void)
{
    sdk_uart_div_modify(0, UART_CLK_FREQ / 115200);
    xTaskCreate(timerRegTask, (signed char *)"timerRegTask", 1024, NULL, 2, NULL);

    TIMER_FRC1_CTRL_REG = TIMER_CTRL_DIV_256|TIMER_CTRL_INT_EDGE|TIMER_CTRL_RELOAD;
    TIMER_FRC1_LOAD_REG = 0x200000;

    TIMER_FRC2_CTRL_REG = TIMER_CTRL_DIV_256|TIMER_CTRL_INT_EDGE;

    DP_INT_ENABLE_REG |= INT_ENABLE_FRC1|INT_ENABLE_FRC2;
    _xt_isr_attach(INUM_TIMER_FRC1, frc1_handler);
    _xt_isr_unmask(1<<INUM_TIMER_FRC1);
    _xt_isr_attach(INUM_TIMER_FRC2, frc2_handler);
    _xt_isr_unmask(1<<INUM_TIMER_FRC2);

    TIMER_FRC1_CTRL_REG |= TIMER_CTRL_RUN;
    TIMER_FRC2_CTRL_REG |= TIMER_CTRL_RUN;

    dump_timer_regs("timer regs during user_init");
    dump_timer_regs("#2 timer regs during user_init");
    dump_timer_regs("#3 timer regs during user_init");
}
Exemplo n.º 11
0
void hw_timer_init(uint8 req)
{
    if (req == 1) {
        RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
                      FRC1_AUTO_LOAD | DIVDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
    } else {
        RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
                      DIVDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
    }

    _xt_isr_attach(ETS_FRC_TIMER1_INUM, hw_timer_isr_cb, NULL);

    TM1_EDGE_INT_ENABLE();
    _xt_isr_unmask(1 << ETS_FRC_TIMER1_INUM);
}
Exemplo n.º 12
0
/*
 * See header file for description.
 */
portBASE_TYPE xPortStartScheduler( void )
{
    _xt_isr_attach(INUM_SOFT, SV_ISR);
    _xt_isr_unmask(BIT(INUM_SOFT));

    /* Initialize system tick timer interrupt and schedule the first tick. */
    sdk__xt_tick_timer_init();

    vTaskSwitchContext();

    sdk__xt_int_exit();

    /* Should not get here as the tasks are now running! */
    return pdTRUE;
}
Exemplo n.º 13
0
void uart_main_init(int baud_rate) {
#ifndef RTOS_SDK
  system_os_task(rx_task, TASK_PRIORITY, rx_task_queue, RXTASK_QUEUE_LEN);
#endif

  if (baud_rate != 0) {
    uart_div_modify(0, UART_CLK_FREQ / baud_rate);
  }

#ifndef RTOS_SDK
  ETS_UART_INTR_ATTACH(rx_isr, 0);
  ETS_INTR_ENABLE(ETS_UART_INUM);
#else
  _xt_isr_attach(ETS_UART_INUM, rx_isr, 0);
  _xt_isr_unmask(1 << ETS_UART_INUM);
#endif
}
Exemplo n.º 14
0
static void uart0_rx_init(void)
{
    int trig_lvl = 1;
    uart0_sem = xSemaphoreCreateCounting(UART0_RX_SIZE, 0);

    _xt_isr_attach(INUM_UART, uart0_rx_handler);
    _xt_isr_unmask(1 << INUM_UART);

    // reset the rx fifo
    uint32_t conf = UART(UART0).CONF0;
    UART(UART0).CONF0 = conf | UART_CONF0_RXFIFO_RESET;
    UART(UART0).CONF0 = conf & ~UART_CONF0_RXFIFO_RESET;

    // set rx fifo trigger
    UART(UART0).CONF1 |= (trig_lvl & UART_CONF1_RXFIFO_FULL_THRESHOLD_M) << UART_CONF1_RXFIFO_FULL_THRESHOLD_S;

    // clear all interrupts
    UART(UART0).INT_CLEAR = 0x1ff;

    // enable rx_interrupt
    UART(UART0).INT_ENABLE = UART_INT_ENABLE_RXFIFO_FULL;

    inited = true;
}
Exemplo n.º 15
0
void pwm_init(uint8_t npins, uint8_t* pins)
{
    /* Assert number of pins is correct */
    if (npins > MAX_PWM_PINS)
    {
        printf("Incorrect number of PWM pins (%d)\n", npins);
        return;
    }

    /* Initialize */
    pwmInfo._maxLoad = 0;
    pwmInfo._onLoad = 0;
    pwmInfo._offLoad = 0;
    pwmInfo._step = PERIOD_ON;

    /* Save pins information */
    pwmInfo.usedPins = npins;

    uint8_t i = 0;
    for (; i < npins; ++i)
    {
        pwmInfo.pins[i].pin = pins[i];

        /* configure GPIOs */
        gpio_enable(pins[i], GPIO_OUTPUT);
    }

    /* Stop timers and mask interrupts */
    pwm_stop();

    /* set up ISRs */
    _xt_isr_attach(INUM_TIMER_FRC1, frc1_interrupt_handler);

    /* Flag not running */
    pwmInfo.running = 0;
}
Exemplo n.º 16
0
//Initialize I2S subsystem for DMA circular buffer use
void ICACHE_FLASH_ATTR i2sInit() {
	int x, y;
	
	underrunCnt=0;
	
	//First, take care of the DMA buffers.
	for (y=0; y<I2SDMABUFCNT; y++) {
		//Allocate memory for this DMA sample buffer.
		i2sBuf[y]=malloc(I2SDMABUFLEN*4);
		//Clear sample buffer. We don't want noise.
		for (x=0; x<I2SDMABUFLEN; x++) {
			i2sBuf[y][x]=0;
		}
	}

	//Reset DMA
	SET_PERI_REG_MASK(SLC_CONF0, SLC_RXLINK_RST|SLC_TXLINK_RST);
	CLEAR_PERI_REG_MASK(SLC_CONF0, SLC_RXLINK_RST|SLC_TXLINK_RST);

	//Clear DMA int flags
	SET_PERI_REG_MASK(SLC_INT_CLR,  0xffffffff);
	CLEAR_PERI_REG_MASK(SLC_INT_CLR,  0xffffffff);

	//Enable and configure DMA
	CLEAR_PERI_REG_MASK(SLC_CONF0, (SLC_MODE<<SLC_MODE_S));
	SET_PERI_REG_MASK(SLC_CONF0,(1<<SLC_MODE_S));
	SET_PERI_REG_MASK(SLC_RX_DSCR_CONF,SLC_INFOR_NO_REPLACE|SLC_TOKEN_NO_REPLACE);
	CLEAR_PERI_REG_MASK(SLC_RX_DSCR_CONF, SLC_RX_FILL_EN|SLC_RX_EOF_MODE | SLC_RX_FILL_MODE);


	//Initialize DMA buffer descriptors in such a way that they will form a circular
	//buffer.
	for (x=0; x<I2SDMABUFCNT; x++) {
		i2sBufDesc[x].owner=1;
		i2sBufDesc[x].eof=1;
		i2sBufDesc[x].sub_sof=0;
		i2sBufDesc[x].datalen=I2SDMABUFLEN*4;
		i2sBufDesc[x].blocksize=I2SDMABUFLEN*4;
		i2sBufDesc[x].buf_ptr=(uint32_t)&i2sBuf[x][0];
		i2sBufDesc[x].unused=0;
		i2sBufDesc[x].next_link_ptr=(int)((x<(I2SDMABUFCNT-1))?(&i2sBufDesc[x+1]):(&i2sBufDesc[0]));
	}
	
	//Feed dma the 1st buffer desc addr
	//To send data to the I2S subsystem, counter-intuitively we use the RXLINK part, not the TXLINK as you might
	//expect. The TXLINK part still needs a valid DMA descriptor, even if it's unused: the DMA engine will throw
	//an error at us otherwise. Just feed it any random descriptor.
	CLEAR_PERI_REG_MASK(SLC_TX_LINK,SLC_TXLINK_DESCADDR_MASK);
	SET_PERI_REG_MASK(SLC_TX_LINK, ((uint32)&i2sBufDesc[1]) & SLC_TXLINK_DESCADDR_MASK); //any random desc is OK, we don't use TX but it needs something valid
	CLEAR_PERI_REG_MASK(SLC_RX_LINK,SLC_RXLINK_DESCADDR_MASK);
	SET_PERI_REG_MASK(SLC_RX_LINK, ((uint32)&i2sBufDesc[0]) & SLC_RXLINK_DESCADDR_MASK);

	//Attach the DMA interrupt
	_xt_isr_attach(ETS_SLC_INUM, (_xt_isr)slc_isr, NULL);
	//Enable DMA operation intr
	WRITE_PERI_REG(SLC_INT_ENA,  SLC_RX_EOF_INT_ENA);
	//clear any interrupt flags that are set
	WRITE_PERI_REG(SLC_INT_CLR, 0xffffffff);
	///enable DMA intr in cpu
	_xt_isr_unmask(1<<ETS_SLC_INUM);

	//We use a queue to keep track of the DMA buffers that are empty. The ISR will push buffers to the back of the queue,
	//the mp3 decode will pull them from the front and fill them. For ease, the queue will contain *pointers* to the DMA
	//buffers, not the data itself. The queue depth is one smaller than the amount of buffers we have, because there's
	//always a buffer that is being used by the DMA subsystem *right now* and we don't want to be able to write to that
	//simultaneously.
	dmaQueue=xQueueCreate(I2SDMABUFCNT-1, sizeof(int*));

	//Start transmission
	SET_PERI_REG_MASK(SLC_TX_LINK, SLC_TXLINK_START);
	SET_PERI_REG_MASK(SLC_RX_LINK, SLC_RXLINK_START);

//----

	//Init pins to i2s functions
	PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_I2SO_DATA);
	PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_I2SO_WS);
#ifndef USE_ESP01_MODULE
	PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_I2SO_BCK);
#else
	GPIO_AS_INPUT(1<<15);
	PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_GPIO15);
#endif
	//Enable clock to i2s subsystem
	i2c_writeReg_Mask_def(i2c_bbpll, i2c_bbpll_en_audio_clock_out, 1);

	//Reset I2S subsystem
	CLEAR_PERI_REG_MASK(I2SCONF,I2S_I2S_RESET_MASK);
	SET_PERI_REG_MASK(I2SCONF,I2S_I2S_RESET_MASK);
	CLEAR_PERI_REG_MASK(I2SCONF,I2S_I2S_RESET_MASK);

	//Select 16bits per channel (FIFO_MOD=0), no DMA access (FIFO only)
	CLEAR_PERI_REG_MASK(I2S_FIFO_CONF, I2S_I2S_DSCR_EN|(I2S_I2S_RX_FIFO_MOD<<I2S_I2S_RX_FIFO_MOD_S)|(I2S_I2S_TX_FIFO_MOD<<I2S_I2S_TX_FIFO_MOD_S));
	//Enable DMA in i2s subsystem
	SET_PERI_REG_MASK(I2S_FIFO_CONF, I2S_I2S_DSCR_EN);

	//tx/rx binaureal
	CLEAR_PERI_REG_MASK(I2SCONF_CHAN, (I2S_TX_CHAN_MOD<<I2S_TX_CHAN_MOD_S)|(I2S_RX_CHAN_MOD<<I2S_RX_CHAN_MOD_S));

	//Clear int
	SET_PERI_REG_MASK(I2SINT_CLR,   I2S_I2S_TX_REMPTY_INT_CLR|I2S_I2S_TX_WFULL_INT_CLR|
			I2S_I2S_RX_WFULL_INT_CLR|I2S_I2S_PUT_DATA_INT_CLR|I2S_I2S_TAKE_DATA_INT_CLR);
	CLEAR_PERI_REG_MASK(I2SINT_CLR, I2S_I2S_TX_REMPTY_INT_CLR|I2S_I2S_TX_WFULL_INT_CLR|
			I2S_I2S_RX_WFULL_INT_CLR|I2S_I2S_PUT_DATA_INT_CLR|I2S_I2S_TAKE_DATA_INT_CLR);

	//trans master&rece slave,MSB shift,right_first,msb right
	CLEAR_PERI_REG_MASK(I2SCONF, I2S_TRANS_SLAVE_MOD|
						(I2S_BITS_MOD<<I2S_BITS_MOD_S)|
						(I2S_BCK_DIV_NUM <<I2S_BCK_DIV_NUM_S)|
						(I2S_CLKM_DIV_NUM<<I2S_CLKM_DIV_NUM_S));
	SET_PERI_REG_MASK(I2SCONF, I2S_RIGHT_FIRST|I2S_MSB_RIGHT|I2S_RECE_SLAVE_MOD|
						I2S_RECE_MSB_SHIFT|I2S_TRANS_MSB_SHIFT|
						((16&I2S_BCK_DIV_NUM )<<I2S_BCK_DIV_NUM_S)|
						((7&I2S_CLKM_DIV_NUM)<<I2S_CLKM_DIV_NUM_S));


	//No idea if ints are needed...
	//clear int
	SET_PERI_REG_MASK(I2SINT_CLR,   I2S_I2S_TX_REMPTY_INT_CLR|I2S_I2S_TX_WFULL_INT_CLR|
			I2S_I2S_RX_WFULL_INT_CLR|I2S_I2S_PUT_DATA_INT_CLR|I2S_I2S_TAKE_DATA_INT_CLR);
	CLEAR_PERI_REG_MASK(I2SINT_CLR,   I2S_I2S_TX_REMPTY_INT_CLR|I2S_I2S_TX_WFULL_INT_CLR|
			I2S_I2S_RX_WFULL_INT_CLR|I2S_I2S_PUT_DATA_INT_CLR|I2S_I2S_TAKE_DATA_INT_CLR);
	//enable int
	SET_PERI_REG_MASK(I2SINT_ENA,   I2S_I2S_TX_REMPTY_INT_ENA|I2S_I2S_TX_WFULL_INT_ENA|
	I2S_I2S_RX_REMPTY_INT_ENA|I2S_I2S_TX_PUT_DATA_INT_ENA|I2S_I2S_RX_TAKE_DATA_INT_ENA);

	//Start transmission
	SET_PERI_REG_MASK(I2SCONF,I2S_I2S_TX_START);
}
Exemplo n.º 17
0
int esp_uart_init(struct esp_uart_config *cfg) {
  static int int_attached = 0;
  if (cfg == NULL || !esp_uart_validate_config(cfg)) return 0;
  WRITE_PERI_REG(UART_INT_ENA(cfg->uart_no), 0);

  struct esp_uart_state *us = s_us[cfg->uart_no];
  if (us != NULL) {
    s_us[cfg->uart_no] = NULL;
    esp_uart_deinit(us);
  }

  us = calloc(1, sizeof(*us));
  us->cfg = cfg;
  cs_rbuf_init(&us->rx_buf, cfg->rx_buf_size);
  cs_rbuf_init(&us->tx_buf, cfg->tx_buf_size);

  uart_div_modify(cfg->uart_no, UART_CLK_FREQ / cfg->baud_rate);

  if (cfg->uart_no == 0) {
    PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
    PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
    if (cfg->swap_rxtx_ctsrts) {
      SET_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
                        PERI_IO_UART0_PIN_SWAP);
    } else {
      CLEAR_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
                          PERI_IO_UART0_PIN_SWAP);
    }
  } else {
    PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO2_U);
    PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
    if (cfg->swap_rxtx_ctsrts) {
      SET_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
                        PERI_IO_UART1_PIN_SWAP);
    } else {
      CLEAR_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
                          PERI_IO_UART1_PIN_SWAP);
    }
  }

  unsigned int conf0 = 0b011100; /* 8-N-1 */
  if (cfg->tx_fc_ena) {
    conf0 |= UART_TX_FLOW_EN;
    PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_U0CTS);
  }
  WRITE_PERI_REG(UART_CONF0(cfg->uart_no), conf0);

  unsigned int conf1 = cfg->rx_fifo_full_thresh;
  conf1 |= (cfg->tx_fifo_empty_thresh << 8);
  if (cfg->rx_fifo_alarm >= 0) {
    conf1 |= UART_RX_TOUT_EN | ((cfg->rx_fifo_alarm & 0x7f) << 24);
  }
  if (cfg->rx_fc_ena && cfg->rx_fifo_fc_thresh > 0) {
    /* UART_RX_FLOW_EN will be set in uart_start. */
    conf1 |= ((cfg->rx_fifo_fc_thresh & 0x7f) << 16);
    PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS);
  }
  WRITE_PERI_REG(UART_CONF1(cfg->uart_no), conf1);

  if (cfg->status_interval_ms > 0) {
    os_timer_disarm(&us->status_timer);
    os_timer_setfn(&us->status_timer, esp_uart_print_status, us);
    os_timer_arm(&us->status_timer, cfg->status_interval_ms, 1 /* repeat */);
  }

  /* Start with TX and RX ints disabled. */
  WRITE_PERI_REG(UART_INT_ENA(cfg->uart_no), UART_INFO_INTS);

  s_us[cfg->uart_no] = us;
  if (!int_attached) {
#ifdef RTOS_SDK
    _xt_isr_attach(ETS_UART_INUM, (void *) esp_uart_isr, NULL);
    _xt_isr_unmask(1 << ETS_UART_INUM);
#else
    ETS_UART_INTR_ATTACH(esp_uart_isr, NULL);
    ETS_INTR_ENABLE(ETS_UART_INUM);
#endif
    int_attached = 1;
  }
  return 1;
}
Exemplo n.º 18
0
void
UART_intr_handler_register(void *fn, void *arg)
{
    _xt_isr_attach(ETS_UART_INUM, fn, arg);
}