/**************************************************************************//**
* @brief Initializes the XCOMM board. The Rx and Tx path are disabled.
*
* @param pDefInit - pointer to initialization structure
*
* @return If success, return 0
* if error, return -1
******************************************************************************/
int32_t XCOMM_Init(XCOMM_DefaultInit* pDefInit)
{
/* Local variables */
uint32_t enableCommMux;
uint32_t ps7Interface = 0;
/* Reset the XCOMM state variables */
int32_t i = 0;
int8_t* pData = (int8_t*)&XCOMM_State;
for(i = 0; i < sizeof(XCOMM_State); i++)
{
pData[i] = 0;
}
/* Initialize the SPI communication */
switch(pDefInit->carrierBoard)
{
case XILINX_ZC702:
ps7Interface = 1;
case XILINX_KC705:
case XILINX_VC707:
enableCommMux = 1;
break;
case DIGILENT_ZED:
pDefInit->fmcPort = FMC_HPC;
case XILINX_ML605:
default:
enableCommMux = 0;
break;
}
XCOMM_boardFmcPort = enableCommMux ? FMC_HPC : pDefInit->fmcPort;
if(SPI_Init(pDefInit->fmcPort, enableCommMux, ps7Interface) < 0)
return -1;
/* Initialize the AD9548 */
if(ad9548_setup() < 0)
return -1;
/* Initialize the AD9523 */
if(ad9523_setup() < 0)
return -1;
/* Initialize the Rx ADF4351 */
if(adf4351_setup(ADF4351_RX_CHANNEL) < 0)
return -1;
/* Initialize the Tx ADF4351 */
if(adf4351_setup(ADF4351_TX_CHANNEL) < 0)
return -1;
/* Read the calibration data from the EEPROM */
if(EEPROM_GetCalData((uint8_t*)XCOMM_calData, &XCOMM_calDataSize, XCOMM_boardFmcPort) < 0)
return -1;
return 0;
}
/**************************************************************************//**
* @brief Initializes the XCOMM board
*
* @param pDefInit - pointer to initialization structure
*
* @return If success, return 0
* if error, return -1
******************************************************************************/
int32_t XCOMM_Init(XCOMM_DefaultInit* pDefInit)
{
/* Local variables */
uint32_t enableCommMux;
/* Reset the XCOMM state variables */
int32_t i = 0;
int8_t* pData = (int8_t*)&XCOMM_State;
for(i = 0; i < sizeof(XCOMM_State); i++)
{
pData[i] = 0;
}
/* Initialize the SPI communication */
switch(pDefInit->carrierBoard)
{
case XILINX_KC705:
case XILINX_VC707:
case XILINX_ZC702:
enableCommMux = 1;
break;
case DIGILENT_ZED:
pDefInit->fmcPort = FMC_HPC;
case XILINX_ML605:
default:
enableCommMux = 0;
break;
}
XCOMM_boardFmcPort = enableCommMux ? FMC_HPC : pDefInit->fmcPort;
if(SPI_Init(pDefInit->fmcPort, enableCommMux) < 0)
return -1;
/* Initialize the AD9548 */
if(ad9548_setup() < 0)
return -1;
/* Initialize the AD9523 */
if(ad9523_setup() < 0)
return -1;
if(XCOMM_SetAdcSamplingRate(pDefInit->adcSamplingRate) < 0)
return -1;
if(XCOMM_SetDacSamplingRate(pDefInit->dacSamplingRate) < 0)
return -1;
/* Initialize the Rx ADF4351 */
if(adf4351_setup(ADF4351_RX_CHANNEL) < 0)
return -1;
if(XCOMM_SetRxFrequency(pDefInit->rxFrequency) < 0)
return -1;
/* Initialize the Tx ADF4351 */
if(adf4351_setup(ADF4351_TX_CHANNEL) < 0)
return -1;
if(XCOMM_SetTxFrequency(pDefInit->txFrequency) < 0)
return -1;
/* Initialize the AD9122 */
DAC_Core_Init(pDefInit->fmcPort);
if(ad9122_setup() < 0)
return -1;
/* Initialize the AD9643 */
ADC_Core_Init(pDefInit->fmcPort);
if(ad9643_setup() < 0)
return -1;
/* Initialize the AD8366 */
if(ad8366_setup() < 0)
return -1;
if(XCOMM_SetRxGain(pDefInit->rxGain1000) < 0)
return -1;
/* Read the calibration data from the EEPROM */
if(EEPROM_GetCalData((uint8_t*)XCOMM_calData, &XCOMM_calDataSize, XCOMM_boardFmcPort) < 0)
return -1;
return 0;
}
/***************************************************************************//**
* @brief main
*******************************************************************************/
int main(void)
{
jesd204b_gt_state jesd204b_gt_st;
jesd204b_state jesd204b_st;
daq2_gpio_ctl(GPIO_BASEADDR);
ad9523_setup(SPI_DEVICE_ID, 0, ad9523_pdata_lpc);
ad9144_setup(SPI_DEVICE_ID, 1, default_ad9144_init_param);
jesd204b_st.lanesync_enable = 1;
jesd204b_st.scramble_enable = 1;
jesd204b_st.sysref_always_enable = 0;
jesd204b_st.frames_per_multiframe = 32;
jesd204b_st.bytes_per_frame = 1;
jesd204b_st.subclass = 1;
jesd204b_setup(AD9144_JESD_BASEADDR, jesd204b_st);
ad9680_setup(SPI_DEVICE_ID, 2);
jesd204b_st.lanesync_enable = 1;
jesd204b_st.scramble_enable = 1;
jesd204b_st.sysref_always_enable = 0;
jesd204b_st.frames_per_multiframe = 32;
jesd204b_st.bytes_per_frame = 1;
jesd204b_st.subclass = 1;
jesd204b_setup(AD9680_JESD_BASEADDR, jesd204b_st);
jesd204b_gt_st.use_cpll = 0;
jesd204b_gt_st.rx_sys_clk_sel = 3;
jesd204b_gt_st.rx_out_clk_sel = 4;
jesd204b_gt_st.tx_sys_clk_sel = 3;
jesd204b_gt_st.tx_out_clk_sel = 4;
jesd204b_gt_setup(DAQ2_GT_BASEADDR, jesd204b_gt_st);
jesd204b_gt_clk_enable(JESD204B_GT_TX);
jesd204b_gt_clk_enable(JESD204B_GT_RX);
jesd204b_gt_clk_synchronize(JESD204B_GT_TX);
jesd204b_gt_clk_synchronize(JESD204B_GT_RX);
dac_setup(AD9144_CORE_BASEADDR);
dds_set_frequency(0, 5000000);
dds_set_phase(0, 0);
dds_set_scale(0, 500000);
dds_set_frequency(1, 5000000);
dds_set_phase(1, 0);
dds_set_scale(1, 500000);
dds_set_frequency(2, 5000000);
dds_set_phase(2, 90000);
dds_set_scale(2, 500000);
dds_set_frequency(3, 5000000);
dds_set_phase(3, 90000);
dds_set_scale(3, 500000);
adc_setup(AD9680_CORE_BASEADDR, AD9680_DMA_BASEADDR, 2);
xil_printf("Done.\n\r");
return 0;
}
