/*
* FUNCTION
* adc_sche_measure
*
* DESCRIPTION
* This function is to measure ADC channel.
*
* CALLS
*
* PARAMETERS
* adc_sche_id: logical channel id
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* None
*/
void adc_sche_measure(void* msg_ptr)
{
MeasParameter *adc_param = (MeasParameter *)msg_ptr;
#if ( (defined(MT6205B))||defined(MT6226M) || (defined(MT6218))|| (defined(MT6218B))|| (defined(MT6219))|| (defined(MT6217))|| (defined(MT6225))|| (defined(MT6228))|| (defined(MT6229))|| (defined(MT6230))|| (defined(MT6226))|| (defined(MT6227)))
#ifdef BMT_DEBUG
//dbg_printWithTime("mea,%d..\r\n",adc_param->adc_logic_id);
#endif
#if 0
/* under construction !*/
/* under construction !*/
#endif
adc_parameters[adc_param->adc_logic_id].adc_sche_event_id = NULL;
if (adc_parameters[adc_param->adc_logic_id].conti_measure)
{
#if !defined(__CHARGER_WITH_IMMEDIMATE_ADC__)
kal_uint32 savedMask;
savedMask = SaveAndSetIRQMask();
adc_sync_mode_on = KAL_TRUE;
adc_pwrdown_disable();
DRV_Reg(AUXADC_SYNC) |= (1<<adc_param->adc_phy_id);
RestoreIRQMask(savedMask);
#endif
adc_sche_rw_status |= (1 << adc_param->adc_logic_id);
adc_sche_set_timer(adc_param->adc_logic_id,1,adc_sche_readback);
}
#endif /*MT6205B,MT6218, MT6218B*/
}
/*
* FUNCTION
* ADC_GetData2Meta
*
* DESCRIPTION
* This function is called by META, and return the sum value.
*
* CALLS
*
* PARAMETERS
* sel : selection of input signal source(0-4)
* meacount: measure count
*
* RETURNS
* return the average value of ADC output
*
* GLOBALS AFFECTED
* None
*/
kal_uint32 ADC_GetData2Meta(kal_uint8 sel, kal_uint16 meacount)
{
#if defined(DRV_ADC_NOT_EXIST)
return 0;
#endif // #if defined(DRV_ADC_NOT_EXIST)
#ifndef DRV_ADC_NOT_EXIST
kal_uint32 index;
kal_uint32 sum=0;
#ifdef __MULTI_BOOT__
ADC_Factory_Boot_check();
#endif /*__MULTI_BOOT__*/
//DRVPDN_Disable(DRVPDN_CON2,DRVPDN_CON2_AUXADC,PDN_ADC);
//adc_pwrdown_disable();
#if defined(__DRV_ADC_SYNC_META__)
if(SW_SEC_0 == INT_SW_SecVersion()) //MT6250 E1
{
adcsche_adc_measure_en(KAL_TRUE);
adc_pwrdown_disable();
for(index=meacount;index!=0;index--)
{
sum += (kal_uint32)ADC_Sync_GetData(sel);
}
adc_pwrdown_enable();
}
else
{
for(index=meacount;index!=0;index--)
{
sum += (kal_uint32)ADC_GetData(sel);
}
}
#else
for(index=meacount;index!=0;index--)
{
sum += (kal_uint32)ADC_GetData(sel);
}
#endif
//DRVPDN_Enable(DRVPDN_CON2,DRVPDN_CON2_AUXADC,PDN_ADC);
//adc_pwrdown_enable();
return sum;
#endif // #ifndef DRV_ADC_NOT_EXIST
}
void ADC_IMM_Data_on_Booting(kal_uint32 channel, kal_uint32 counts, kal_uint16 *data){
kal_uint32 i,j;
#if defined(DRV_ADC_NOT_EXIST)
return;
#endif // #if defined(DRV_ADC_NOT_EXIST)
// Enalbe ADC power
adc_pwrdown_disable();
#ifndef DRV_ADC_NOT_EXIST
//ASSERT(channel < ADC_MAX_CHANNEL);
adc_channel_number_check(channel);
// Add PMIC ADC measurement circuit turn on here
adcsche_adc_measure_en(KAL_TRUE);
for(j=0;j<counts;j++)
{
#if defined(DRV_ADC_NO_IMM) || defined(FPGA)
DRV_ADC_WriteReg(AUXADC_CTRL,channel);
while(!(DRV_ADC_Reg(AUXADC_STAT) & AUXADC_STAT_RDY));
data += DRV_ADC_Reg(AUXADC_DATA);
#endif // #if defined(DRV_ADC_NO_IMM) || defined(FPGA)
#if defined(DRV_ADC_IMM)
DRV_ADC_WriteReg(AUXADC_IMM, 0);
adc_dummy_read();
DRV_ADC_SetBits(AUXADC_IMM, (1<<channel));
adc_dummy_read(); // make sure the write command is finish
for(i=100; i!=0; i--);
while((DRV_ADC_Reg(AUXADC_CON) & AUXADC_CON_RUN));
*(data+j) = DRV_ADC_Reg(AUXADC_DAT(channel));
#endif // #if defined(DRV_ADC_IMM)
}
// Add PMIC ADC measurement circuit turn off here
#if !defined(DRV_ADC_MODEM_SIDE) //don't write pmu bit to 0
adcsche_adc_measure_en(KAL_FALSE);
#endif
adc_pwrdown_enable();
#endif // #ifndef DRV_ADC_NOT_EXIST
}
void ADC_IMM_Data_on_Booting(kal_uint32 channel, kal_uint32 counts, kal_uint16 *data){
#ifndef DRV_ADC_NOT_EXIST
volatile kal_uint32 i;
kal_uint32 j;
#endif //#ifndef DRV_ADC_NOT_EXIST
#if defined(DRV_ADC_NOT_EXIST)
return;
#endif // #if defined(DRV_ADC_NOT_EXIST)
// Enalbe ADC power
adc_pwrdown_disable();
#ifndef DRV_ADC_NOT_EXIST
ASSERT(channel < ADC_MAX_CHANNEL);
// Add PMIC ADC measurement circuit turn on here
adcsche_adc_measure_en(KAL_TRUE);
for(j=0;j<counts;j++)
{
#if defined(DRV_ADC_NO_IMM) || defined(FPGA)
DRV_ADC_WriteReg(AUXADC_CTRL,channel);
while(!(DRV_ADC_Reg(AUXADC_STAT) & AUXADC_STAT_RDY));
data += DRV_ADC_Reg(AUXADC_DATA);
#endif // #if defined(DRV_ADC_NO_IMM) || defined(FPGA)
#if defined(DRV_ADC_IMM)
DRV_ADC_WriteReg(AUXADC_IMM, 0);
DRV_ADC_SetBits(AUXADC_IMM, (1<<channel));
for(i=100;i!=0;i--); /* delay for avoid reading invalid status bit */
while((DRV_ADC_Reg(AUXADC_CON) & AUXADC_CON_RUN));
*(data+j) = DRV_ADC_Reg(AUXADC_DAT(channel));
#endif // #if defined(DRV_ADC_IMM)
}
// Add PMIC ADC measurement circuit turn off here
#if !defined(DRV_ADC_MODEM_SIDE) //don't write pmu bit to 0
adcsche_adc_measure_en(KAL_FALSE);
#endif
#endif // #ifndef DRV_ADC_NOT_EXIST
}
/*Specific measure function for BMT*/
void bmt_adc_sche_measure(void* msg_ptr)
{
MeasParameter *adc_param = (MeasParameter *)msg_ptr;
static kal_uint8 bmt_measure_count=0;
static kal_uint8 bmt_measure_channels=0;
kal_uint8 index=0;
#if ( (defined(MT6205B))||defined(MT6226M) || (defined(MT6218))|| (defined(MT6218B))|| (defined(MT6219))|| (defined(MT6217))|| (defined(MT6225))|| (defined(MT6228))|| (defined(MT6229))|| (defined(MT6230))|| (defined(MT6226))|| (defined(MT6227)))
adc_parameters[adc_param->adc_logic_id].adc_sche_event_id = NULL;
if (adc_parameters[adc_param->adc_logic_id].conti_measure)
{
bmt_measure_count++;
adc_sche_rw_status |= (1 << adc_param->adc_logic_id);
bmt_measure_channels|= (1<<adc_param->adc_phy_id);
if(bmt_measure_count>=BMT_MAX_CHANNEL)
{
#if !defined(__CHARGER_WITH_IMMEDIMATE_ADC__)
kal_uint32 savedMask;
savedMask = SaveAndSetIRQMask();
adc_sync_mode_on = KAL_TRUE;
adc_pwrdown_disable();
DRV_Reg(AUXADC_SYNC) |= bmt_measure_channels;
RestoreIRQMask(savedMask);
#endif
for(index=0;index<BMT_MAX_CHANNEL;index++)
{
adc_sche_set_timer(bmt_bmtid_adcscheid[index],1,bmt_adc_sche_readback);
}
bmt_measure_count=0;
bmt_measure_channels=0;
}
}
#endif /*MT6205B,MT6218,MT6218B*/
}
kal_uint16 ADC_GetData(kal_uint8 sel)
{
#if defined(DRV_ADC_NOT_EXIST)
return 0;
#endif // #if defined(DRV_ADC_NOT_EXIST)
#ifndef DRV_ADC_NOT_EXIST
#if defined(DRV_ADC_MODEM_SIDE)
kal_uint32 saved_current_time = 0;
#endif
kal_uint16 data;
#if !defined(ADC_REMOVE_IRQMASK)
kal_uint32 savedMask;
#endif //#if !defined(ADC_REMOVE_IRQMASK)
#if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA)
kal_uint32 savedMask2;
#endif // #if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA)
adc_channel_number_check(sel);
#if defined(DRV_ADC_NO_IMM) || defined(FPGA)
ADCSAVEANDSETIRQMASK(savedMask); //savedMask = SaveAndSetIRQMask();
adc_pwrdown_disable();
#ifndef DRV_ADC_MODEM_SIDE
DRV_ADC_WriteReg(AUXADC_CTRL,sel);
#endif // #ifndef DRV_ADC_MODEM_SIDE
adc_imm_mode_cnt++;
ADCRESTOREIRQMASK(savedMask); //RestoreIRQMask(savedMask);
while(!(DRV_ADC_Reg(AUXADC_STAT) & AUXADC_STAT_RDY));
data = DRV_ADC_Reg(AUXADC_DATA);
#endif /*(DRV_ADC_NO_IMM,FPGA)*/
#if defined(DRV_ADC_IMM)
ADCSAVEANDSETIRQMASK(savedMask); //savedMask = SaveAndSetIRQMask();
adc_imm_mode_cnt++;
adcsche_adc_measure_en(KAL_TRUE);
ADCRESTOREIRQMASK(savedMask); //RestoreIRQMask(savedMask);
#if defined(__DRV_ADC_PMIC_TURN_ON_MEASURE_DELAY__)
if((ADC_VBAT == sel) ||
(ADC_VISENSE == sel) ||
(ADC_VCHARGER == sel))
{
kal_sleep_task(1); //delay 2 frames for HEPHAESTUS68 need delay to measure
}
#endif //#if defined(__DRV_ADC_PMIC_TURN_ON_MEASURE_DELAY__)
ADCSAVEANDSETIRQMASK(savedMask); //savedMask = SaveAndSetIRQMask();
adc_pwrdown_disable();
#if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA)
{
savedMask2 = SaveAndSetIRQMask();
}
#endif // #if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA)
#if defined(DRV_ADC_VCHARGER_EXTEND_READING)
if(ADC_VCHARGER == sel)
{
DRV_ADC_SetBits(MIX_ABB_base + 0x0b00,0x01f0); //extend to MAX ticks while reading
}
#endif
#ifdef DRV_ADC_SET_CLR
DRV_ADC_SetBits(AUXADC_CON1_CLR, (1<<sel));
DRV_ADC_SetBits(AUXADC_CON1_SET, (1<<sel));
#else
DRV_ADC_WriteReg(AUXADC_IMM, 0);
adc_dummy_read();
//DRV_ADC_Reg(AUXADC_IMM) = 0;
DRV_ADC_SetBits(AUXADC_IMM, (1<<sel));
//DRV_ADC_Reg(AUXADC_IMM) |= (1<<sel);
#endif
ADCRESTOREIRQMASK(savedMask); //RestoreIRQMask(savedMask);
#if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA)
{
volatile kal_uint32 tmp_32;
for (tmp_32=20;tmp_32!=0;tmp_32--){
;
}
}
#endif // #if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA)
#if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA)
{
RestoreIRQMask(savedMask2);
}
#endif // #if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA)
#if !defined(DRV_MISC_IGNORE_ADC_RUN_STATUS_CHECK)
#if defined(DRV_ADC_MODEM_SIDE)
{
kal_uint32 i;
for(i=100;i!=0;i--);
while((DRV_ADC_Reg(AUXADC_DAT(sel)) & 0x1000) == 0x1000);
}
#else
adc_check_busy_bit();
#endif
#endif // #if !defined(DRV_MISC_IGNORE_ADC_RUN_STATUS_CHECK)
data = (DRV_ADC_Reg(AUXADC_DAT(sel)) & 0x0FFF);
#if defined(DRV_ADC_MODEM_SIDE)
saved_current_time = drv_get_current_time();
while(drv_get_duration_tick(saved_current_time, drv_get_current_time()) <= 2) // 64us
{
;// Polling 32K reference clock
}
#endif
#endif /*DRV_ADC_IMM*/
ADCSAVEANDSETIRQMASK(savedMask); //savedMask = SaveAndSetIRQMask();
adc_imm_mode_cnt--;
if ((((kal_uint16)adc_imm_mode_cnt) == 0) && (((kal_bool)adc_sync_mode_on) == KAL_FALSE))
{
adc_pwrdown_enable();
}
ADCRESTOREIRQMASK(savedMask); //RestoreIRQMask(savedMask);
ADCSAVEANDSETIRQMASK(savedMask); //savedMask = SaveAndSetIRQMask();
if ((((kal_uint16)adc_imm_mode_cnt) == 0) && (((kal_bool)adc_sync_mode_on) == KAL_FALSE))
{
#if !defined(DRV_ADC_MODEM_SIDE) //don't write pmu bit to 0
adcsche_adc_measure_en(KAL_FALSE);
#endif
}
ADCRESTOREIRQMASK(savedMask); //RestoreIRQMask(savedMask);
return data;
#endif // #ifndef DRV_ADC_NOT_EXIST
}
DCL_STATUS DclHADC_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
{
switch (cmd)
{
case ADC_CMD_IMM_MEASURE:
{
ADC_CTRL_IMM_MEASURE_T *prIMMMeasure;
prIMMMeasure = &(data->rADCImmMeasure);
if (!dcl_hadc_power_state){
ASSERT(0);
return STATUS_FAIL;
}
prIMMMeasure->u2ADCValue = ADC_IMM_Data(prIMMMeasure->u2Channel);
return STATUS_OK;
}
case ADC_CMD_SYNC_MEASURE:
{
ADC_CTRL_SYNC_MEASURE_T *prSYNCMeasure;
prSYNCMeasure = &(data->rADCSyncMeasure);
if (!dcl_hadc_power_state){
ASSERT(0);
return STATUS_FAIL;
}
prSYNCMeasure->u2ADCValue = ADC_SYNC_Data(prSYNCMeasure->u2Channel);
return STATUS_OK;
}
case ADC_CMD_TDMA_SYNC_SETUP:
{
#if defined(DRV_ADC_FULL_FUNC)
ADC_CTRL_TDMA_SYNC_SETUP_T *prTDMASyncSetup;
prTDMASyncSetup = &(data->rADCTDMASyncSetup);
adc_tdma_time_setup(prTDMASyncSetup->u2Event0, prTDMASyncSetup->u2Event1);
return STATUS_OK;
#else // #if defined(DRV_ADC_FULL_FUNC)
// Not supported
return STATUS_INVALID_CMD;
#endif
}
case ADC_CMD_POWER:
{
ADC_CTRL_POWER_T *prPower;
prPower = &(data->rADCPower);
if (prPower->fgEnable == DCL_TRUE){
// Enable ADC power
adc_pwrdown_disable();
dcl_hadc_power_state = KAL_TRUE;
}else{
// Disable ADC power
dcl_hadc_power_state = KAL_FALSE;
adc_pwrdown_enable();
}
return STATUS_OK;
}
case ADC_CMD_GET_DATA_2_META:
{
ADC_CTRL_GET_DATA_2_META_T *prGetData2Meta;
prGetData2Meta = &(data->rADCGetData2Meta);
prGetData2Meta->u4ADCData = ADC_GetData2Meta(prGetData2Meta->u1Channel, prGetData2Meta->u2MeaCount);
return STATUS_OK;
}
case ADC_CMD_GET_DATA:
{
ADC_CTRL_GET_DATA_T *prGetData;
prGetData = &(data->rADCGetData);
prGetData->u4ADCData = ADC_GetData(prGetData->u1Channel);
return STATUS_OK;
}
case ADC_CMD_GET_META_DATA:
{
ADC_CTRL_GET_META_DATA_T *prGetMetaData;
prGetMetaData = &(data->rADCGetMetaData);
prGetMetaData->u4ADCData = ADC_GetMeaData(prGetMetaData->u1Channel, prGetMetaData->u2MeaCount);
return STATUS_OK;
}
case ADC_CMD_GET_MAX_PHYSICAL_CH:
{
ADC_CTRL_GET_MAX_PHYSICAL_CH_T *prGetMaxPhyCh;
prGetMaxPhyCh = &(data->rADCGetMaxPhyCh);
prGetMaxPhyCh->u4Adc_max_ch = ADC_MAX_CHANNEL;
return STATUS_OK;
}
case ADC_CMD_GET_IMM_DATA_ON_BOOTING:
{
ADC_CTRL_GET_IMM_DATA_ON_BOOTING_T *prGetImmDataOnBooting;
prGetImmDataOnBooting = &(data->rGetImmDataOnBooting);
ADC_IMM_Data_on_Booting((kal_uint32)prGetImmDataOnBooting->u4Channel, (kal_uint32)prGetImmDataOnBooting->u4MeaCount, (kal_uint16 *)prGetImmDataOnBooting->u2ADCData);
return STATUS_OK;
}
default:
return STATUS_INVALID_CMD;
}
//return STATUS_FAIL;
}