static void init_isr_tbl()
{
int i;
for (i = 0; i < ISR_NUM; i++) {
isr_tbl[i] = default_routine;
}
add_isr(0, clock_routine);
add_isr(1, keyboard_routine);
}
void
afscattach(struct device *pdp, struct device *dp, void *auxp)
{
struct siop_softc *sc = (struct siop_softc *)dp;
struct zbus_args *zap;
siop_regmap_p rp;
struct scsipi_adapter *adapt = &sc->sc_adapter;
struct scsipi_channel *chan = &sc->sc_channel;
printf("\n");
zap = auxp;
if (zap->manid == 514 && zap->prodid == 84)
sc->sc_siopp = rp = (siop_regmap_p)((char *)zap->va +
0x00800000);
else
sc->sc_siopp = rp = ztwomap(0xdd0040);
/*
* CTEST7 = 80 [disable burst]
*/
sc->sc_clock_freq = 50; /* Clock = 50 MHz */
sc->sc_ctest7 = SIOP_CTEST7_CDIS;
sc->sc_dcntl = SIOP_DCNTL_EA;
/*
* Fill in the scsipi_adapter.
*/
memset(adapt, 0, sizeof(*adapt));
adapt->adapt_dev = &sc->sc_dev;
adapt->adapt_nchannels = 1;
adapt->adapt_openings = 7;
adapt->adapt_max_periph = 1;
adapt->adapt_request = siop_scsipi_request;
adapt->adapt_minphys = siop_minphys;
/*
* Fill in the scsipi_channel.
*/
memset(chan, 0, sizeof(*chan));
chan->chan_adapter = adapt;
chan->chan_bustype = &scsi_bustype;
chan->chan_channel = 0;
chan->chan_ntargets = 8;
chan->chan_nluns = 8;
chan->chan_id = 7;
siopinitialize(sc);
sc->sc_isr.isr_intr = afsc_dmaintr;
sc->sc_isr.isr_arg = sc;
sc->sc_isr.isr_ipl = 2;
add_isr (&sc->sc_isr);
/*
* attach all scsi units on us
*/
config_found(dp, chan, scsiprint);
}
void
lpt_supio_attach(device_t parent, device_t self, void *aux)
{
struct lptsupio_softc *sc = device_private(self);
struct lpt_softc *lsc = &sc->sc_lpt;
int iobase;
bus_space_tag_t iot;
struct supio_attach_args *supa = aux;
/*
* We're living on a superio chip.
*/
lsc->sc_dev = self;
iobase = supa->supio_iobase;
iot = lsc->sc_iot = supa->supio_iot;
sc->sc_intack = (void *)supa->supio_arg;
aprint_normal(" port 0x%04x ipl %d\n", iobase, supa->supio_ipl);
if (bus_space_map(iot, iobase, LPT_NPORTS, 0, &lsc->sc_ioh)) {
aprint_error_dev(self, "io mapping failed\n");
return;
}
lpt_attach_subr(lsc);
sc->sc_isr.isr_intr = lpt_supio_intr;
sc->sc_isr.isr_arg = sc;
sc->sc_isr.isr_ipl = supa->supio_ipl;
add_isr(&sc->sc_isr);
}
void
bah_zbus_attach(device_t parent, device_t self, void *aux)
{
struct bah_zbus_softc *bsc = device_private(self);
struct bah_softc *sc = &bsc->sc_bah;
struct zbus_args *zap = aux;
sc->sc_dev = self;
#if (defined(BAH_DEBUG) && (BAH_DEBUG > 2))
printf("\n%s: attach(0x%p, 0x%p, 0x%p)\n",
device_xname(self), parent, self, aux);
#endif
bsc->sc_bst.base = (bus_addr_t)zap->va;
bsc->sc_bst.absm = &amiga_bus_stride_2;
sc->sc_bst_r = &bsc->sc_bst;
sc->sc_regs = bsc->sc_bst.base + 0x4000;
sc->sc_bst_m = &bsc->sc_bst;
sc->sc_mem = bsc->sc_bst.base + 0x8000;
sc->sc_reset = bah_zbus_reset;
bah_attach_subr(sc);
bsc->sc_isr.isr_intr = bahintr;
bsc->sc_isr.isr_arg = sc;
bsc->sc_isr.isr_ipl = 2;
add_isr(&bsc->sc_isr);
}
void
mgnscattach(device_t parent, device_t self, void *aux)
{
struct siop_softc *sc = device_private(self);
struct zbus_args *zap;
siop_regmap_p rp;
struct scsipi_adapter *adapt = &sc->sc_adapter;
struct scsipi_channel *chan = &sc->sc_channel;
sc->sc_dev = self;
printf("\n");
zap = aux;
sc->sc_siopp = rp = (siop_regmap_p)((char *)zap->va + 0x8000);
/*
* CTEST7 = TT1
*/
sc->sc_clock_freq = 33; /* Clock = 33 MHz */
sc->sc_ctest7 = SIOP_CTEST7_TT1;
sc->sc_dcntl = 0x00;
sc->sc_siop_si = softint_establish(SOFTINT_BIO,
(void (*)(void *))siopintr, sc);
/*
* Fill in the scsipi_adapter.
*/
memset(adapt, 0, sizeof(*adapt));
adapt->adapt_dev = self;
adapt->adapt_nchannels = 1;
adapt->adapt_openings = 7;
adapt->adapt_max_periph = 1;
adapt->adapt_request = siop_scsipi_request;
adapt->adapt_minphys = siop_minphys;
/*
* Fill in the scsipi_channel.
*/
memset(chan, 0, sizeof(*chan));
chan->chan_adapter = adapt;
chan->chan_bustype = &scsi_bustype;
chan->chan_channel = 0;
chan->chan_ntargets = 8;
chan->chan_nluns = 8;
chan->chan_id = 7;
siopinitialize(sc);
sc->sc_isr.isr_intr = mgnsc_dmaintr;
sc->sc_isr.isr_arg = sc;
sc->sc_isr.isr_ipl = 6;
add_isr (&sc->sc_isr);
/*
* attach all scsi units on us
*/
config_found(self, chan, scsiprint);
}
/*
* Install interface into kernel networking data structures.
*/
void
ne_xsurf_attach(device_t parent, device_t self, void *aux)
{
struct ne_xsurf_softc *zsc = device_private(self);
struct ne2000_softc *nsc = &zsc->sc_ne2000;
struct dp8390_softc *dsc = &nsc->sc_dp8390;
struct xsurfbus_attach_args *xap = aux;
bus_space_tag_t nict = &zsc->sc_bst;
bus_space_handle_t nich;
bus_space_tag_t asict = nict;
bus_space_handle_t asich;
dsc->sc_dev = self;
dsc->sc_mediachange = rtl80x9_mediachange;
dsc->sc_mediastatus = rtl80x9_mediastatus;
dsc->init_card = rtl80x9_init_card;
dsc->sc_media_init = rtl80x9_media_init;
zsc->sc_bst.base = xap->xaa_base;
zsc->sc_bst.absm = &amiga_bus_stride_2;
aprint_normal("\n");
/* Map i/o space. */
if (bus_space_map(nict, NE_XSURF_NICBASE,
NE_XSURF_NPORTS, 0, &nich)) {
aprint_error_dev(self, "can't map nic i/o space\n");
return;
}
if (bus_space_subregion(nict, nich, NE2000_ASIC_OFFSET,
NE_XSURF_ASICSIZE, &asich)) {
aprint_error_dev(self, "can't map asic i/o space\n");
return;
}
dsc->sc_regt = nict;
dsc->sc_regh = nich;
nsc->sc_asict = asict;
nsc->sc_asich = asich;
/* This interface is always enabled. */
dsc->sc_enabled = 1;
/*
* Do generic NE2000 attach. This will read the station address
* from the EEPROM.
*/
ne2000_attach(nsc, NULL);
zsc->sc_isr.isr_intr = dp8390_intr;
zsc->sc_isr.isr_arg = dsc;
zsc->sc_isr.isr_ipl = 2;
add_isr(&zsc->sc_isr);
}
void
melody_attach(device_t parent, device_t self, void *aux)
{
struct melody_softc *sc;
struct zbus_args *zap;
bus_space_tag_t iot;
bus_space_handle_t ioh;
sc = device_private(self);
zap = aux;
sc->sc_bst_leftbyte.base = (u_long)zap->va + 0;
sc->sc_bst_leftbyte.absm = &amiga_bus_stride_2;
sc->sc_intack = (uint8_t *)zap->va + 0xc000;
/* set up board specific part in sc_tav */
iot = &sc->sc_bst_leftbyte;
if (bus_space_map(iot, 0, 128, 0, &ioh)) {
panic("melody: cant bus_space_map");
/* NOTREACHED */
}
sc->sc_tav.sc_dev = self;
sc->sc_tav.sc_iot = iot;
sc->sc_tav.sc_ioh = ioh;
sc->sc_tav.sc_pcm_ord = 0;
sc->sc_tav.sc_pcm_18 = 0;
sc->sc_tav.sc_dif = 0;
sc->sc_tav.sc_pcm_div = 12;
mutex_init(&sc->sc_tav.sc_lock, MUTEX_DEFAULT, IPL_NONE);
mutex_init(&sc->sc_tav.sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED);
cv_init(&sc->sc_tav.sc_cv, device_xname(self));
/*
* Attach option boards now. They might provide additional
* functionality to our audio part.
*/
/* attach our audio driver */
printf(" #%d", zap->serno);
tms320av110_attach_mi(&sc->sc_tav);
sc->sc_isr.isr_ipl = 6;
sc->sc_isr.isr_arg = &sc->sc_tav;
sc->sc_isr.isr_intr = tms320av110_intr;
add_isr(&sc->sc_isr);
}
static void
slhci_zbus_attach(device_t parent, device_t self, void *aux)
{
struct slhci_zbus_softc *zsc;
struct slhci_softc *sc;
struct zbus_args *zap;
bus_space_tag_t iot;
bus_space_handle_t ioh;
zap = aux;
zsc = device_private(self);
sc = &zsc->sc_sc;
sc->sc_dev = self;
sc->sc_bus.ub_hcpriv = sc;
zsc->sc_bst.base = (bus_addr_t)zap->va;
zsc->sc_bst.absm = &amiga_bus_stride_1;
iot = &zsc->sc_bst;
aprint_normal(": Thylacine USB Host Controller\n");
if (bus_space_map(iot, THYLACINE_SLHCI_ADDR_OFFSET, THYLACINE_SIZE, 0,
&ioh)) {
aprint_error_dev(sc->sc_dev, "can't map the bus\n");
}
slhci_preinit(sc, slhci_zbus_enable_power, iot, ioh, 500,
THYLACINE_SLHCI_DATA_STRIDE);
/* Attach interrupt routine. */
zsc->sc_isr.isr_intr = slhci_intr;
zsc->sc_isr.isr_arg = sc;
zsc->sc_isr.isr_ipl = 6;
add_isr(&zsc->sc_isr);
slhci_attach(sc);
}
void
empscattach(device_t parent, device_t self, void *aux)
{
volatile u_char *rp;
struct sci_softc *sc = device_private(self);
struct zbus_args *zap;
struct scsipi_adapter *adapt = &sc->sc_adapter;
struct scsipi_channel *chan = &sc->sc_channel;
printf("\n");
zap = aux;
rp = (u_char *)zap->va + 0x5000;
sc->sc_dev = self;
sc->sci_data = rp;
sc->sci_odata = rp;
sc->sci_icmd = rp + 0x10;
sc->sci_mode = rp + 0x20;
sc->sci_tcmd = rp + 0x30;
sc->sci_bus_csr = rp + 0x40;
sc->sci_sel_enb = rp + 0x40;
sc->sci_csr = rp + 0x50;
sc->sci_dma_send = rp + 0x50;
sc->sci_idata = rp + 0x60;
sc->sci_trecv = rp + 0x60;
sc->sci_iack = rp + 0x70;
sc->sci_irecv = rp + 0x70;
sc->sc_isr.isr_intr = empsc_intr;
sc->sc_isr.isr_arg = sc;
sc->sc_isr.isr_ipl = 2;
add_isr(&sc->sc_isr);
scireset(sc);
/*
* Fill in the scsipi_adapter.
*/
memset(adapt, 0, sizeof(*adapt));
adapt->adapt_dev = self;
adapt->adapt_nchannels = 1;
adapt->adapt_openings = 7;
adapt->adapt_max_periph = 1;
adapt->adapt_request = sci_scsipi_request;
adapt->adapt_minphys = sci_minphys;
/*
* Fill in the scsipi_channel.
*/
memset(chan, 0, sizeof(*chan));
chan->chan_adapter = adapt;
chan->chan_bustype = &scsi_bustype;
chan->chan_channel = 0;
chan->chan_ntargets = 8;
chan->chan_nluns = 8;
chan->chan_id = 7;
/*
* attach all scsi units on us
*/
config_found(self, chan, scsiprint);
}
void
ed_zbus_attach(device_t parent, device_t self, void *aux)
{
struct ed_zbus_softc *zsc = device_private(self);
struct dp8390_softc *sc = &zsc->sc_dp8390;
struct zbus_args *zap = aux;
bus_space_handle_t promh;
bus_addr_t memaddr, promaddr, regaddr;
int i;
zsc->sc_bst.base = (bus_addr_t)zap->va;
zsc->sc_bst.absm = &amiga_bus_stride_1;
if (zap->manid == HYDRA_MANID) {
regaddr = HYDRA_REGADDR;
memaddr = HYDRA_MEMADDR;
promaddr = HYDRA_PROMADDR;
} else {
regaddr = ASDG_REGADDR;
memaddr = ASDG_MEMADDR;
promaddr = ASDG_PROMADDR;
}
sc->sc_dev = self;
sc->sc_regt = &zsc->sc_bst;
sc->sc_buft = &zsc->sc_bst;
if (bus_space_map(sc->sc_regt, regaddr, 0x20, 0, &sc->sc_regh)) {
aprint_error_dev(self, "can't map i/o space\n");
return;
}
if (bus_space_map(sc->sc_buft, memaddr, ED_ZBUS_MEMSIZE, 0,
&sc->sc_bufh)) {
aprint_error_dev(self, "can't map buffer space\n");
return;
}
/* SRAM buffer size is always 16K */
sc->mem_start = 0;
sc->mem_size = ED_ZBUS_MEMSIZE;
/*
* Read the ethernet address from the PROM.
* Interrupts must be inactive when reading the PROM, as the
* interrupt line is shared with one of its address lines.
*/
NIC_PUT(sc->sc_regt, sc->sc_regh, ED_P0_IMR, 0x00);
NIC_PUT(sc->sc_regt, sc->sc_regh, ED_P0_ISR, 0xff);
if (bus_space_map(&zsc->sc_bst, promaddr, ETHER_ADDR_LEN * 2, 0,
&promh) == 0) {
for (i = 0; i < ETHER_ADDR_LEN; i++)
sc->sc_enaddr[i] =
bus_space_read_1(&zsc->sc_bst, promh, i * 2);
bus_space_unmap(&zsc->sc_bst, promh, ETHER_ADDR_LEN * 2);
}
/* Initialize sc_reg_map[]. Registers have stride 2 on the bus. */
for (i = 0; i < 16; i++)
sc->sc_reg_map[i] = i << 1;
/*
* Set 2 word FIFO threshold, no auto-init Remote DMA,
* byte order 68k, word-wide DMA xfers.
*/
sc->dcr_reg = ED_DCR_FT0 | ED_DCR_WTS | ED_DCR_LS | ED_DCR_BOS;
/* Remote DMA abort .*/
sc->cr_proto = ED_CR_RD2;
/*
* Override all functions which deal with the buffer, because
* this implementation only allows 16-bit buffer accesses.
*/
sc->test_mem = ed_zbus_test_mem;
sc->read_hdr = ed_zbus_read_hdr;
sc->ring_copy = ed_zbus_ring_copy;
sc->write_mbuf = ed_zbus_write_mbuf;
sc->sc_flags = device_cfdata(self)->cf_flags;
sc->is790 = 0;
sc->sc_media_init = dp8390_media_init;
sc->sc_enabled = 1;
/* Do generic DS8390/WD83C690 config. */
if (dp8390_config(sc)) {
bus_space_unmap(sc->sc_buft, sc->sc_bufh, ED_ZBUS_MEMSIZE);
bus_space_unmap(sc->sc_regt, sc->sc_regh, 0x10);
return;
}
/* establish level 2 interrupt handler */
zsc->sc_isr.isr_intr = dp8390_intr;
zsc->sc_isr.isr_arg = sc;
zsc->sc_isr.isr_ipl = 2;
add_isr(&zsc->sc_isr);
}
void
wstscattach(struct device *pdp, struct device *dp, void *auxp)
{
volatile u_char *rp;
struct sci_softc *sc = (struct sci_softc *)dp;
struct zbus_args *zap;
struct scsipi_adapter *adapt = &sc->sc_adapter;
struct scsipi_channel *chan = &sc->sc_channel;
printf("\n");
zap = auxp;
rp = zap->va;
/*
* set up 5380 register pointers
* (Needs check on which Supra board this is - for now,
* just do the WordSync)
*/
sc->sci_data = rp + 0;
sc->sci_odata = rp + 0;
sc->sci_icmd = rp + 2;
sc->sci_mode = rp + 4;
sc->sci_tcmd = rp + 6;
sc->sci_bus_csr = rp + 8;
sc->sci_sel_enb = rp + 8;
sc->sci_csr = rp + 10;
sc->sci_dma_send = rp + 10;
sc->sci_idata = rp + 12;
sc->sci_trecv = rp + 12;
sc->sci_iack = rp + 14;
sc->sci_irecv = rp + 14;
if (supradma_pseudo == 2) {
sc->dma_xfer_in = (int(*)(struct sci_softc *, int, u_char *, int))wstsc_dma_xfer_in2;
sc->dma_xfer_out = (int(*)(struct sci_softc *, int, u_char *, int))wstsc_dma_xfer_out2;
}
else if (supradma_pseudo == 1) {
sc->dma_xfer_in = wstsc_dma_xfer_in;
sc->dma_xfer_out = wstsc_dma_xfer_out;
}
sc->sc_isr.isr_intr = wstsc_intr;
sc->sc_isr.isr_arg = sc;
sc->sc_isr.isr_ipl = 2;
add_isr(&sc->sc_isr);
scireset(sc);
/*
* Fill in the scsipi_adapter.
*/
memset(adapt, 0, sizeof(*adapt));
adapt->adapt_dev = &sc->sc_dev;
adapt->adapt_nchannels = 1;
adapt->adapt_openings = 7;
adapt->adapt_max_periph = 1;
adapt->adapt_request = sci_scsipi_request;
adapt->adapt_minphys = sci_minphys;
/*
* Fill in the scsipi_channel.
*/
memset(chan, 0, sizeof(*chan));
chan->chan_adapter = adapt;
chan->chan_bustype = &scsi_bustype;
chan->chan_channel = 0;
chan->chan_ntargets = 8;
chan->chan_nluns = 8;
chan->chan_id = 7;
/*
* attach all scsi units on us
*/
config_found(dp, chan, scsiprint);
}
void
drscattach(device_t parent, device_t self, void *aux)
{
struct siop_softc *sc = device_private(self);
siop_regmap_p rp;
struct scsipi_adapter *adapt = &sc->sc_adapter;
struct scsipi_channel *chan = &sc->sc_channel;
printf("\n");
sc->sc_dev = self;
sc->sc_siopp = rp = (siop_regmap_p)(DRCCADDR+PAGE_SIZE*DRSCSIPG);
/*
* CTEST7 = TT1
*/
sc->sc_clock_freq = 50; /* Clock = 50MHz */
sc->sc_ctest7 = 0x02;
sc->sc_siop_si = softint_establish(SOFTINT_BIO,
(void (*)(void *))siopintr, sc);
/*
* Fill in the scsipi_adapter.
*/
memset(adapt, 0, sizeof(*adapt));
adapt->adapt_dev = self;
adapt->adapt_nchannels = 1;
adapt->adapt_openings = 7;
adapt->adapt_max_periph = 1;
adapt->adapt_request = siop_scsipi_request;
adapt->adapt_minphys = siop_minphys;
/*
* Fill in the scsipi_channel.
*/
memset(chan, 0, sizeof(*chan));
chan->chan_adapter = adapt;
chan->chan_bustype = &scsi_bustype;
chan->chan_channel = 0;
chan->chan_ntargets = 8;
chan->chan_nluns = 8;
chan->chan_id = 7;
siopinitialize(sc);
#if 0
sc->sc_isr.isr_intr = drsc_dmaintr;
sc->sc_isr.isr_arg = sc;
sc->sc_isr.isr_ipl = 4;
add_isr(&sc->sc_isr);
#else
drsc_softc = sc;
single_inst_bclr_b(*draco_intpen, DRIRQ_SCSI);
single_inst_bset_b(*draco_intena, DRIRQ_SCSI);
#endif
/*
* attach all scsi units on us
*/
config_found(self, chan, scsiprint);
}
void
mfcattach(device_t parent, device_t self, void *aux)
{
struct mfc_softc *scc;
struct zbus_args *zap;
struct mfc_args ma;
int unit;
struct mfc_regs *rp;
zap = aux;
printf ("\n");
scc = device_private(self);
scc->sc_dev = self;
unit = device_unit(self);
scc->sc_regs = rp = zap->va;
if (zap->prodid == 18)
scc->mfc_iii = 3;
scc->clk_frq = scc->mfc_iii ? 230400 : 115200;
rp->du_opcr = 0x00; /* configure output port? */
rp->du_btrst = 0x0f; /* clear modem lines */
rp->du_ivr = 0; /* IVR */
rp->du_imr = 0; /* IMR */
rp->du_acr = 0xe0; /* baud rate generate set 2 */
rp->du_ctur = 0;
rp->du_ctlr = 4;
rp->du_csra = 0xcc; /* clock select = 38400 */
rp->du_cra = 0x10; /* reset mode register ptr */
rp->du_cra = 0x20;
rp->du_cra = 0x30;
rp->du_cra = 0x40;
rp->du_mr1a = 0x93; /* MRA1 */
rp->du_mr2a = 0x17; /* MRA2 */
rp->du_csrb = 0xcc; /* clock select = 38400 */
rp->du_crb = 0x10; /* reset mode register ptr */
rp->du_crb = 0x20;
rp->du_crb = 0x30;
rp->du_crb = 0x40;
rp->du_mr1b = 0x93; /* MRB1 */
rp->du_mr2b = 0x17; /* MRB2 */
rp->du_cra = 0x05; /* enable A Rx & Tx */
rp->du_crb = 0x05; /* enable B Rx & Tx */
scc->sc_isr.isr_intr = mfcintr;
scc->sc_isr.isr_arg = scc;
scc->sc_isr.isr_ipl = 6;
add_isr(&scc->sc_isr);
/* configure ports */
memcpy(&ma.zargs, zap, sizeof(struct zbus_args));
ma.subdev = "mfcs";
ma.unit = unit * 2;
config_found(self, &ma, mfcprint);
ma.unit = unit * 2 + 1;
config_found(self, &ma, mfcprint);
ma.subdev = "mfcp";
ma.unit = unit;
config_found(self, &ma, mfcprint);
}
void
atzscattach(device_t parent, device_t self, void *aux)
{
volatile struct sdmac *rp;
struct sbic_softc *sc = device_private(self);
struct zbus_args *zap;
struct scsipi_adapter *adapt = &sc->sc_adapter;
struct scsipi_channel *chan = &sc->sc_channel;
zap = aux;
sc->sc_dev = self;
sc->sc_cregs = rp = zap->va;
/*
* disable ints and reset bank register
*/
rp->CNTR = CNTR_PDMD;
amiga_membarrier();
rp->DAWR = DAWR_ATZSC;
amiga_membarrier();
sc->sc_enintr = atzsc_enintr;
sc->sc_dmago = atzsc_dmago;
sc->sc_dmanext = atzsc_dmanext;
sc->sc_dmastop = atzsc_dmastop;
sc->sc_dmacmd = 0;
/*
* only 24 bit mem.
*/
sc->sc_flags |= SBICF_BADDMA;
sc->sc_dmamask = ~0x00ffffff;
#if 0
/*
* If the users kva space is not ztwo try and allocate a bounce buffer.
* XXX this needs to change if we move to multiple memory segments.
*/
if (kvtop(sc) & sc->sc_dmamask) {
sc->sc_dmabuffer = (char *)alloc_z2mem(MAXPHYS * 8); /* XXX */
if (isztwomem(sc->sc_dmabuffer))
printf(" bounce pa 0x%x", kvtop(sc->sc_dmabuffer));
else if (sc->sc_dmabuffer)
printf(" bounce pa 0x%x",
PREP_DMA_MEM(sc->sc_dmabuffer));
}
#endif
sc->sc_sbic.sbic_asr_p = (volatile unsigned char *)rp + 0x91;
sc->sc_sbic.sbic_value_p = (volatile unsigned char *)rp + 0x93;
sc->sc_clkfreq = sbic_clock_override ? sbic_clock_override : 77;
printf(": dmamask 0x%lx\n", ~sc->sc_dmamask);
/*
* Fill in the scsipi_adapter.
*/
memset(adapt, 0, sizeof(*adapt));
adapt->adapt_dev = self;
adapt->adapt_nchannels = 1;
adapt->adapt_openings = 7;
adapt->adapt_max_periph = 1;
adapt->adapt_request = sbic_scsipi_request;
adapt->adapt_minphys = sbic_minphys;
/*
* Fill in the scsipi_channel.
*/
memset(chan, 0, sizeof(*chan));
chan->chan_adapter = adapt;
chan->chan_bustype = &scsi_bustype;
chan->chan_channel = 0;
chan->chan_ntargets = 8;
chan->chan_nluns = 8;
chan->chan_id = 7;
sbicinit(sc);
sc->sc_isr.isr_intr = atzsc_dmaintr;
sc->sc_isr.isr_arg = sc;
sc->sc_isr.isr_ipl = 2;
add_isr (&sc->sc_isr);
/*
* attach all scsi units on us
*/
config_found(self, chan, scsiprint);
}
void
wdc_buddha_attach(device_t parent, device_t self, void *aux)
{
struct wdc_buddha_softc *sc;
struct zbus_args *zap;
int nchannels;
int ch;
sc = device_private(self);
sc->sc_wdcdev.sc_atac.atac_dev = self;
zap = aux;
sc->ba = zap->va;
sc->sc_iot.base = (bus_addr_t)sc->ba;
sc->sc_iot.absm = &amiga_bus_stride_4swap;
nchannels = 2;
if (zap->prodid == 42) {
aprint_normal(": Catweasel Z2\n");
nchannels = 3;
} else if (zap->serno == 0)
aprint_normal(": Buddha\n");
else
aprint_normal(": Buddha Flash\n");
/* XXX pio mode setting not implemented yet. */
sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16;
sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = nchannels;
wdc_allocate_regs(&sc->sc_wdcdev);
for (ch = 0; ch < nchannels; ch++) {
struct ata_channel *cp;
struct wdc_regs *wdr;
int i;
cp = &sc->channels[ch];
sc->wdc_chanarray[ch] = cp;
cp->ch_channel = ch;
cp->ch_atac = &sc->sc_wdcdev.sc_atac;
cp->ch_queue =
malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT);
if (cp->ch_queue == NULL) {
aprint_error_dev(self,
"can't allocate memory for command queue\n");
return;
}
cp->ch_ndrive = 2;
/*
* XXX According to the Buddha docs, we should use a method
* array that adds 0x40 to the address for byte accesses, to
* get the slow timing for command accesses, and the 0x00
* offset for the word (fast) accesses. This will be
* reconsidered when implementing setting the timing.
*
* XXX We also could consider to abuse the 32bit capability, or
* 32bit accesses to the words (which will read in two words)
* for better performance.
* -is
*/
wdr = CHAN_TO_WDC_REGS(cp);
wdr->cmd_iot = &sc->sc_iot;
if (bus_space_map(wdr->cmd_iot, 0x210+ch*0x80, 8, 0,
&wdr->cmd_baseioh)) {
aprint_error_dev(self, "couldn't map cmd registers\n");
return;
}
wdr->ctl_iot = &sc->sc_iot;
if (bus_space_map(wdr->ctl_iot, 0x250+ch*0x80, 2, 0,
&wdr->ctl_ioh)) {
bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 8);
aprint_error_dev(self, "couldn't map ctl registers\n");
return;
}
for (i = 0; i < WDC_NREG; i++) {
if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
i, i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
aprint_error_dev(self,
"couldn't subregion cmd regs\n");
return;
}
}
wdc_init_shadow_regs(cp);
wdcattach(cp);
}
sc->sc_isr.isr_intr = wdc_buddha_intr;
sc->sc_isr.isr_arg = sc;
sc->sc_isr.isr_ipl = 2;
add_isr (&sc->sc_isr);
sc->ba[0xfc0] = 0; /* enable interrupts */
}
int atari_scsi_detect (Scsi_Host_Template *host)
{
static int called = 0;
struct Scsi_Host *instance;
if (!MACH_IS_ATARI ||
(!ATARIHW_PRESENT(ST_SCSI) && !ATARIHW_PRESENT(TT_SCSI)) ||
called)
return( 0 );
host->proc_dir = &proc_scsi_atari;
atari_scsi_reg_read = IS_A_TT() ? atari_scsi_tt_reg_read :
atari_scsi_falcon_reg_read;
atari_scsi_reg_write = IS_A_TT() ? atari_scsi_tt_reg_write :
atari_scsi_falcon_reg_write;
/* setup variables */
host->can_queue =
(setup_can_queue > 0) ? setup_can_queue :
IS_A_TT() ? ATARI_TT_CAN_QUEUE : ATARI_FALCON_CAN_QUEUE;
host->cmd_per_lun =
(setup_cmd_per_lun > 0) ? setup_cmd_per_lun :
IS_A_TT() ? ATARI_TT_CMD_PER_LUN : ATARI_FALCON_CMD_PER_LUN;
/* Force sg_tablesize to 0 on a Falcon! */
host->sg_tablesize =
!IS_A_TT() ? ATARI_FALCON_SG_TABLESIZE :
(setup_sg_tablesize >= 0) ? setup_sg_tablesize : ATARI_TT_SG_TABLESIZE;
if (setup_hostid >= 0)
host->this_id = setup_hostid;
else {
/* use 7 as default */
host->this_id = 7;
/* Test if a host id is set in the NVRam */
if (ATARIHW_PRESENT(TT_CLK)) {
unsigned char sum = 0, b;
int i;
/* Make checksum */
for( i = 14; i < 62; ++i )
sum += RTC_READ(i);
if (/* NV-Ram checksum valid? */
RTC_READ(62) == sum && RTC_READ(63) == ~sum &&
/* Arbitration enabled? (for TOS) */
(b = RTC_READ( 30 )) & 0x80) {
host->this_id = b & 7;
}
}
}
#ifdef SUPPORT_TAGS
if (setup_use_tagged_queuing < 0)
setup_use_tagged_queuing = DEFAULT_USE_TAGGED_QUEUING;
#endif
/* If running on a Falcon and if there's TT-Ram (i.e., more than one
* memory block, since there's always ST-Ram in a Falcon), then allocate a
* STRAM_BUFFER_SIZE byte dribble buffer for transfers from/to alternative
* Ram.
*/
if (MACH_IS_ATARI && ATARIHW_PRESENT(ST_SCSI) &&
!ATARIHW_PRESENT(EXTD_DMA) && boot_info.num_memory > 1) {
atari_dma_buffer = scsi_init_malloc(STRAM_BUFFER_SIZE,
GFP_ATOMIC | GFP_DMA);
atari_dma_phys_buffer = VTOP( atari_dma_buffer );
atari_dma_orig_addr = 0;
}
instance = scsi_register (host, sizeof (struct NCR5380_hostdata));
atari_scsi_host = instance;
instance->irq = IS_A_TT() ? IRQ_TT_MFP_SCSI : IRQ_MFP_FSCSI;
atari_scsi_reset_boot();
NCR5380_init (instance, 0);
if (IS_A_TT()) {
/* This int is actually "pseudo-slow", i.e. it acts like a slow
* interrupt after having cleared the pending flag for the DMA
* interrupt. */
add_isr(IRQ_TT_MFP_SCSI, scsi_tt_intr, IRQ_TYPE_SLOW,
NULL, "SCSI NCR5380");
tt_mfp.active_edge |= 0x80; /* SCSI int on L->H */
#ifdef REAL_DMA
tt_scsi_dma.dma_ctrl = 0;
atari_dma_residual = 0;
#endif /* REAL_DMA */
if (is_medusa) {
/* While the read overruns (described by Drew Eckhardt in
* NCR5380.c) never happened on TTs, they do in fact on the Medusa
* (This was the cause why SCSI didn't work right for so long
* there.) Since handling the overruns slows down a bit, I turned
* the #ifdef's into a runtime condition.
*
* In principle it should be sufficient to do max. 1 byte with
* PIO, but there is another problem on the Medusa with the DMA
* rest data register. So 'atari_read_overruns' is currently set
* to 4 to avoid having transfers that aren't a multiple of 4. If
* the rest data bug is fixed, this can be lowered to 1.
*/
atari_read_overruns = 4;
}
}
else { /* ! IS_A_TT */
/* Nothing to do for the interrupt: the ST-DMA is initialized
* already by atari_init_INTS()
*/
#ifdef REAL_DMA
atari_dma_residual = 0;
atari_dma_active = 0;
atari_dma_stram_mask = (ATARIHW_PRESENT(EXTD_DMA) ? 0x00000000
: 0xff000000);
#endif
}
printk(KERN_INFO "scsi%d: options CAN_QUEUE=%d CMD_PER_LUN=%d SCAT-GAT=%d "
#ifdef SUPPORT_TAGS
"TAGGED-QUEUING=%s "
#endif
"HOSTID=%d",
instance->host_no, instance->hostt->can_queue,
instance->hostt->cmd_per_lun,
instance->hostt->sg_tablesize,
#ifdef SUPPORT_TAGS
setup_use_tagged_queuing ? "yes" : "no",
#endif
instance->hostt->this_id );
NCR5380_print_options (instance);
printk ("\n");
called = 1;
return( 1 );
}
/*
* attach to the grfbus (zbus)
*/
void
grfulattach(device_t parent, device_t self, void *aux)
{
static struct grf_ul_softc congrf;
struct device temp;
struct zbus_args *zap;
struct grf_softc *gp;
struct grf_ul_softc *gup;
zap = aux;
if (self == NULL) {
gup = &congrf;
gp = &gup->gus_sc;
gp->g_device = &temp;
temp.dv_private = gp;
} else {
gup = device_private(self);
gp = &gup->gus_sc;
gp->g_device = self;
}
if (self != NULL && congrf.gus_sc.g_regkva != 0) {
/*
* inited earlier, just copy (not device struct)
*/
memcpy(&gp->g_display, &congrf.gus_sc.g_display,
(char *)&gup->gus_isr - (char *)&gp->g_display);
/* ...and transfer the isr */
gup->gus_isr.isr_ipl = 2;
gup->gus_isr.isr_intr = ulisr;
gup->gus_isr.isr_arg = (void *)gp;
/*
* To make sure ints are always catched, first add new isr
* then remove old:
*/
add_isr(&gup->gus_isr);
remove_isr(&congrf.gus_isr);
} else {
gp->g_regkva = (void *)zap->va;
gp->g_fbkva = NULL;
gp->g_unit = GRF_ULOWELL_UNIT;
gp->g_flags = GF_ALIVE;
gp->g_mode = ul_mode;
#if NITE > 0
gp->g_conpri = grful_cnprobe();
#endif
gp->g_data = NULL;
gup->gus_isr.isr_ipl = 2;
gup->gus_isr.isr_intr = ulisr;
gup->gus_isr.isr_arg = (void *)gp;
add_isr(&gup->gus_isr);
(void)ul_load_code(gp);
(void)ul_load_mon(gp, current_mon);
#if NITE > 0
grful_iteinit(gp);
#endif
}
if (self != NULL)
printf("\n");
/*
* attach grf
*/
amiga_config_found(cfdata, gp->g_device, gp, grfulprint);
}
void
drscattach(struct device *pdp, struct device *dp, void *auxp)
{
struct siop_softc *sc = (struct siop_softc *)dp;
struct zbus_args *zap;
siop_regmap_p rp;
struct scsipi_adapter *adapt = &sc->sc_adapter;
struct scsipi_channel *chan = &sc->sc_channel;
printf("\n");
zap = auxp;
sc->sc_siopp = rp = (siop_regmap_p)(DRCCADDR+PAGE_SIZE*DRSCSIPG);
/*
* CTEST7 = TT1
*/
sc->sc_clock_freq = 50; /* Clock = 50MHz */
sc->sc_ctest7 = 0x02;
alloc_sicallback();
/*
* Fill in the scsipi_adapter.
*/
memset(adapt, 0, sizeof(*adapt));
adapt->adapt_dev = &sc->sc_dev;
adapt->adapt_nchannels = 1;
adapt->adapt_openings = 7;
adapt->adapt_max_periph = 1;
adapt->adapt_request = siop_scsipi_request;
adapt->adapt_minphys = siop_minphys;
/*
* Fill in the scsipi_channel.
*/
memset(chan, 0, sizeof(*chan));
chan->chan_adapter = adapt;
chan->chan_bustype = &scsi_bustype;
chan->chan_channel = 0;
chan->chan_ntargets = 8;
chan->chan_nluns = 8;
chan->chan_id = 7;
siopinitialize(sc);
#if 0
sc->sc_isr.isr_intr = drsc_dmaintr;
sc->sc_isr.isr_arg = sc;
sc->sc_isr.isr_ipl = 4;
add_isr(&sc->sc_isr);
#else
drsc_softc = sc;
single_inst_bclr_b(*draco_intpen, DRIRQ_SCSI);
single_inst_bset_b(*draco_intena, DRIRQ_SCSI);
#endif
/*
* attach all scsi units on us
*/
config_found(dp, chan, scsiprint);
}
static void
pccard_attach(struct device *parent, struct device *myself, void *aux)
{
struct pccard_softc *self = (struct pccard_softc *) myself;
struct pcmciabus_attach_args paa;
vaddr_t pcmcia_base;
vaddr_t i;
printf("\n");
gayle_init();
pcmcia_base = uvm_km_alloc(kernel_map,
GAYLE_PCMCIA_END - GAYLE_PCMCIA_START,
0, UVM_KMF_VAONLY | UVM_KMF_NOWAIT);
if (pcmcia_base == 0) {
printf("attach failed (no virtual memory)\n");
return;
}
for (i = GAYLE_PCMCIA_START; i < GAYLE_PCMCIA_END; i += PAGE_SIZE)
pmap_enter(vm_map_pmap(kernel_map),
i - GAYLE_PCMCIA_START + pcmcia_base, i,
VM_PROT_READ | VM_PROT_WRITE, true);
pmap_update(vm_map_pmap(kernel_map));
/* override the one-byte access methods for I/O space */
pcmio_bs_methods = amiga_bus_stride_1;
pcmio_bs_methods.bsr1 = pcmio_bsr1;
pcmio_bs_methods.bsw1 = pcmio_bsw1;
pcmio_bs_methods.bsrm1 = pcmio_bsrm1;
pcmio_bs_methods.bswm1 = pcmio_bswm1;
pcmio_bs_methods.bsrr1 = pcmio_bsrr1;
pcmio_bs_methods.bswr1 = pcmio_bswr1;
pcmio_bs_methods.bssr1 = pcmio_bssr1;
pcmio_bs_methods.bscr1 = pcmio_bscr1;
reset_card_reg = (u_int8_t *) pcmcia_base +
(GAYLE_PCMCIA_RESET - GAYLE_PCMCIA_START);
self->io_space.base = (bus_addr_t) pcmcia_base +
(GAYLE_PCMCIA_IO_START - GAYLE_PCMCIA_START);
self->io_space.absm = &pcmio_bs_methods;
self->attr_space.base = (bus_addr_t) pcmcia_base +
(GAYLE_PCMCIA_ATTR_START - GAYLE_PCMCIA_START);
self->attr_space.absm = &amiga_bus_stride_1;
/* XXX we should check if the 4M of common memory are actually
* RAM or PCMCIA usable.
* For now, we just do as if the 4M were RAM and make common memory
* point to attribute memory, which is OK for some I/O cards.
*/
self->mem_space.base = (bus_addr_t) pcmcia_base;
self->mem_space.absm = &amiga_bus_stride_1;
self->devs[0].sc = self;
self->devs[0].intr_func = NULL;
self->devs[0].intr_arg = NULL;
self->devs[0].flags = 0;
gayle.pcc_status = 0;
gayle.intreq = 0;
gayle.pcc_config = 0;
gayle.intena &= GAYLE_INT_IDE;
paa.paa_busname = "pcmcia";
paa.pct = &chip_functions;
paa.pch = &self->devs[0];
paa.iobase = 0;
paa.iosize = 0;
self->devs[0].card =
config_found(myself, &paa, simple_devprint);
if (self->devs[0].card == NULL) {
printf("attach failed, config_found() returned NULL\n");
pmap_remove(kernel_map->pmap, pcmcia_base,
pcmcia_base + (GAYLE_PCMCIA_END - GAYLE_PCMCIA_START));
pmap_update(kernel_map->pmap);
uvm_deallocate(kernel_map, pcmcia_base,
GAYLE_PCMCIA_END - GAYLE_PCMCIA_START);
return;
}
self->intr6.isr_intr = pccard_intr6;
self->intr6.isr_arg = self;
self->intr6.isr_ipl = 6;
add_isr(&self->intr6);
self->intr2.isr_intr = pccard_intr2;
self->intr2.isr_arg = self;
self->intr2.isr_ipl = 2;
add_isr(&self->intr2);
if (kthread_create(PRI_NONE, 0, NULL, pccard_kthread, self,
NULL, "pccard")) {
printf("%s: can't create kernel thread\n",
self->sc_dev.dv_xname);
panic("pccard kthread_create() failed");
}
gayle.intena |= GAYLE_INT_DETECT | GAYLE_INT_IREQ;
/* reset the card if it's already there */
if (gayle.pcc_status & GAYLE_CCMEM_DETECT) {
volatile u_int8_t x;
*reset_card_reg = 0x0;
delay(1000);
x = *reset_card_reg;
gayle.pcc_status = GAYLE_CCMEM_WP | GAYLE_CCIO_SPKR;
}
pccard_attach_slot(&self->devs[0]);
}
void
wdc_amiga_attach(device_t parent, device_t self, void *aux)
{
struct wdc_amiga_softc *sc = device_private(self);
struct wdc_regs *wdr;
int i;
aprint_normal("\n");
sc->sc_wdcdev.sc_atac.atac_dev = self;
sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs;
gayle_init();
if (is_a4000()) {
sc->cmd_iot.base = (bus_addr_t) ztwomap(GAYLE_IDE_BASE_A4000 + 2);
} else {
sc->cmd_iot.base = (bus_addr_t) ztwomap(GAYLE_IDE_BASE + 2);
}
sc->cmd_iot.absm = sc->ctl_iot.absm = &amiga_bus_stride_4swap;
wdr->cmd_iot = &sc->cmd_iot;
wdr->ctl_iot = &sc->ctl_iot;
if (bus_space_map(wdr->cmd_iot, 0, 0x40, 0,
&wdr->cmd_baseioh)) {
aprint_error_dev(self, "couldn't map registers\n");
return;
}
for (i = 0; i < WDC_NREG; i++) {
if (bus_space_subregion(wdr->cmd_iot,
wdr->cmd_baseioh, i, i == 0 ? 4 : 1,
&wdr->cmd_iohs[i]) != 0) {
bus_space_unmap(wdr->cmd_iot,
wdr->cmd_baseioh, 0x40);
aprint_error_dev(self, "couldn't map registers\n");
return;
}
}
if (bus_space_subregion(wdr->cmd_iot,
wdr->cmd_baseioh, 0x406, 1, &wdr->ctl_ioh))
return;
sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16;
sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
sc->sc_chanlist[0] = &sc->sc_channel;
sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_chanlist;
sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
sc->sc_wdcdev.wdc_maxdrives = 2;
sc->sc_channel.ch_channel = 0;
sc->sc_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
sc->sc_channel.ch_queue = &sc->sc_chqueue;
wdc_init_shadow_regs(&sc->sc_channel);
sc->sc_isr.isr_intr = wdc_amiga_intr;
sc->sc_isr.isr_arg = sc;
sc->sc_isr.isr_ipl = 2;
add_isr (&sc->sc_isr);
if (!is_a4000())
gayle_intr_enable_set(GAYLE_INT_IDE);
wdcattach(&sc->sc_channel);
}
