void rx_ethernet_isr1 (void *context)
{
struct netif * netif = &TSE1netif;
//Poczekanie na zakoñczenie odbióru ramki ethernetowej z³¹czem po³¹czonym z eth_tse1
while (alt_avalon_sgdma_check_descriptor_status(&rx_descriptor1) != 0)
;
//dl odebranej ramki
pklen = IORD_16DIRECT(&(rx_descriptor1.actual_bytes_transferred),0);
//printf("dlugosc odebranych danych to: %d",pklen);
memcpy(tx_frame,rx_frame1,pklen);
p->payload=tx_frame;
ethernet_input(p,netif);
alt_avalon_sgdma_construct_mem_to_stream_desc( &tx_descriptor, &tx_descriptor_end, (alt_u32 *)tx_frame, pklen-4, 0, 1, 1, 0 );
alt_avalon_sgdma_do_async_transfer( sgdma_tx_dev, &tx_descriptor );
while (alt_avalon_sgdma_check_descriptor_status(&tx_descriptor) != 0);
alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor1, &rx_descriptor_end1, (alt_u32 *)rx_frame1, 0, 0 );
alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev1, &rx_descriptor1 );
p->len=0;
p->tot_len=0;
}
void rx_ethernet_isr (void *context)
{
struct netif * netif = &TSE1netif;
//Poczekanie na zakoñczenie odbioru ramki ethernetowej z³¹czem po³¹czonym z eth_tse
while (alt_avalon_sgdma_check_descriptor_status(&rx_descriptor) != 0)
;
//zapisanie do zmiennej pklen dlugosci odebranej ramki ethernetowej
pklen = IORD_16DIRECT(&(rx_descriptor.actual_bytes_transferred),0);
memcpy(tx_frame,rx_frame,pklen);
p->payload=tx_frame;
// funkcja lwip ethernet_input obslugujaca ramkê Ethernetow¹
ethernet_input(p,netif);
//Wys³anie ramki ethernetowej z³¹czem po³¹czonym z eth_tse1
alt_avalon_sgdma_construct_mem_to_stream_desc( &tx_descriptor1,
&tx_descriptor_end1, (alt_u32 *)tx_frame, pklen-4, 0, 1, 1, 0 );
alt_avalon_sgdma_do_async_transfer( sgdma_tx_dev1, &tx_descriptor1 );
while (alt_avalon_sgdma_check_descriptor_status(&tx_descriptor1) != 0);
//Ponowne skonsturowanie deskryptorów odbiorczych z³¹cza eth_tse
alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor,
&rx_descriptor_end, (alt_u32 *)rx_frame, 0, 0 );
alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev, &rx_descriptor );
//wyzerowanie pól z d³ugociami bufora lwIP
p->len=0;
p->tot_len=0;
}
/**
* funkcja generujaca 1MBdanych testowych i zapisujaca je w pamieci SRAM
*/
void przygotowanie_danych()
{
int k=0;
int sram_adres=0x90000;
int j = 0;
for (j=0 ; j<1024; j++)
{
//Generacja wektorow testowych z dokumentacji NIST
if(j%6==0)
dane[j]=0x54686520;
else if(j%6==1)
dane[j]=0x71756663;
else if(j%6==2)
dane[j]=0x6B206272;
else if(j%6==3)
dane[j]=0x6F776E20;
else if(j%6==4)
dane[j]=0x666F7820;
else if(j%6==5)
dane[j]=0x6A756D70;
}
//Zapis wektorow testowych do pamieci SRAM
while(k<256){
alt_avalon_sgdma_construct_mem_to_mem_desc(&read_descriptor,&read_descriptor_end,(alt_u32 *) *dane,(alt_u32*)sram_adres,(alt_u16)4096,0,0);
alt_avalon_sgdma_do_async_transfer( sgdma_read_3des, &read_descriptor );
while (alt_avalon_sgdma_check_descriptor_status(&read_descriptor) != 0);
sram_adres+=4096;
k++;
}
}
void rx_ethernet_isr1 (void *context)
{
int i;
// Wait until receive descriptor transfer is complete
while (alt_avalon_sgdma_check_descriptor_status(&rx_descriptor1) != 0)
;
// Clear input line before writing
for (i = 0; i < (6 + text_length); i++) {
alt_printf( "%c", 0x08 ); // 0x1024008 --> backspace
}
// Output received text
// alt_printf( "receive> %s\n", rx_frame + 16 );
i=0;
while(rx_frame1[i] != NULL)
{
alt_printf( "%c", rx_frame1[i] );
i++;// 0x1024008 --> backspace
}
// Reprint current input line after the output
//alt_printf( "send> %s", tx_frame + 16 );
// Create new receive sgdma descriptor
alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor1, &rx_descriptor_end1, (alt_u32 *)rx_frame1, 0, 0 );
// Set up non-blocking transfer of sgdma receive descriptor
alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev1, &rx_descriptor1 );
}
/**
* Przeprowadzenie deszyfrowania 1MB danych w pamieci SRAM oraz zapisanie ich
*/
void przeprowadzenie_deszyfrowania_sram()
{
int k=0;
int sram_adres_read=0x90000; //adres do odczytu
int sram_adres_write=sram_adres_read+1048576; //adres do zapisu
while(k<256)
{
alt_avalon_sgdma_construct_mem_to_mem_desc(&read_descriptor,&read_descriptor_end,(alt_u32 *) sram_adres_read,(alt_u32*)*dane,(alt_u16)4096,0,0);
alt_avalon_sgdma_do_async_transfer( sgdma_read_3des, &read_descriptor );
while (alt_avalon_sgdma_check_descriptor_status(&read_descriptor) != 0);
paczka_deszyfrowanie();
alt_avalon_sgdma_construct_mem_to_mem_desc(&read_descriptor,&read_descriptor_end,(alt_u32 *) *wyniki,(alt_u32*)sram_adres_write,(alt_u16)4096,0,0);
alt_avalon_sgdma_do_async_transfer( sgdma_read_3des, &read_descriptor );
while (alt_avalon_sgdma_check_descriptor_status(&read_descriptor) != 0);
sram_adres_read+=4096;
sram_adres_write+=4096;
k++;
}
}
/****************************************************************************************
* Subroutine to read incoming Ethernet frames
****************************************************************************************/
void rx_ethernet_isr (void *context)
{
//Include your code to show the values of the source and destination addresses of the received frame. For example:
//if(in==1){
alt_printf( "Source address: %x,%x, %x, %x, %x, %x \n", rx_frame[8], rx_frame[9],rx_frame[10], rx_frame[11], rx_frame[12], rx_frame[13]);
alt_printf( "destination address: %x,%x, %x, %x, %x, %x \n", rx_frame[2], rx_frame[3],rx_frame[4], rx_frame[5], rx_frame[6], rx_frame[7]);
alt_printf("message length: %x,%x",rx_frame[17],rx_frame[18]);
//}
// Wait until receive descriptor transfer is complete
while (alt_avalon_sgdma_check_descriptor_status(&rx_descriptor) != 0)
;
// Create new receive sgdma descriptor
alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor, &rx_descriptor_end, (alt_u32 *)rx_frame, 0, 0 );
// Set up non-blocking transfer of sgdma receive descriptor
alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev, &rx_descriptor );
}
void rx_ethernet_isr (void *context)
{
int i;
// Wait until receive descriptor transfer is complete
while (alt_avalon_sgdma_check_descriptor_status(&rx_descriptor) != 0)
;
// Clear input line before writing
for (i = 0; i < (6 + text_length); i++) {
alt_printf( "%c", 0x08 ); // 0x1024008 --> backspace
}
// Output received text
// alt_printf( "receive> %s\n", rx_frame + 16 );
i=0;
// Set up non-blocking transfer of sgdma receive descriptor
int speed=alt_tse_mac_get_common_speed( ETH_TSE_BASE);
printf("Currents speed: %i",speed);
printf("\n");
//unsigned int *readtse;
//*readtse=
//volatile int * tse = (int *) ETH_TSE_BASE;
//*(tse + 0x3A)=0x00040000;
//printf("Readtse : %i",readtse);
printf("\n");
printf("odebrano ramke \n");
while(i<342)
{
alt_printf( "%x", rx_frame[i] );
i++;// 0x1024008 --> backspaces
if (rx_frame[i] =='\n')
{
i=1024;
}
}
// Reprint current input line after the outputs
// alt_printf( "send> %s", tx_frame + 16 );
i=0;
/*while (i<7)
{
tx_frame[i]=0x55;
i++;
}
tx_frame[7]=0xD5;*/
while (i<6)
{
tx_frame[i]=0xFF;
i++;
}
tx_frame[6]=0x01;
tx_frame[7]=0x60;
tx_frame[8]=0x6E;
tx_frame[9]=0x11;
tx_frame[10]=0x02;
tx_frame[11]=0x0F;
tx_frame[12]=0x08;
tx_frame[13]=0x00;
i=14;
while (i <88)
{
tx_frame[i]=rx_frame[i+1];
i++;
}
tx_frame[88]='\0';
alt_avalon_sgdma_construct_mem_to_stream_desc( &tx_descriptor, &tx_descriptor_end, (alt_u32 *)tx_frame, 92, 0, 1, 1, 0 );
alt_avalon_sgdma_do_async_transfer( sgdma_tx_dev, &tx_descriptor );
while (alt_avalon_sgdma_check_descriptor_status(&tx_descriptor) != 0);
//ff_tx_eop=1;
alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor, &rx_descriptor_end, (alt_u32 *)rx_frame, 0, 0 );
alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev, &rx_descriptor );
//alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev, &rx_descriptor );
printf("\n");
printf("zakonczono odbior ramki\n");
// Create new receive sgdma descriptor
// alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor, &rx_descriptor_end, (alt_u32 *)rx_frame, 0, 0 );
}