static void fio_reactive_sdio_irq(void)
{
int i;
for (i = 5; i > 0; i--) {
/* Fake SDIO irq can be clear by */
/* re-enable sdio irq bit while SDIO is enable. */
/* If it's fake, it can be clear in 5 times. */
amba_clrbitsw(SD_NISEN_REG, SD_NISEN_CARD);
amba_setbitsw(SD_NISEN_REG, SD_NISEN_CARD);
if ((amba_readw(SD_NIS_REG) & SD_NIS_CARD) == 0) {
break;
}
}
}
/* ==========================================================================*/
void __fio_select_lock(int module)
{
u32 fio_ctr;
u32 fio_dmactr;
fio_ctr = amba_readl(FIO_CTR_REG);
fio_dmactr = amba_readl(FIO_DMACTR_REG);
switch (module) {
case SELECT_FIO_FL:
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_FL;
break;
case SELECT_FIO_XD:
fio_ctr |= FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_XD;
break;
case SELECT_FIO_CF:
fio_ctr &= ~FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_CF;
#if (FIO_SUPPORT_AHB_CLK_ENA == 1)
fio_amb_sd2_disable();
fio_amb_cf_enable();
#endif
break;
case SELECT_FIO_SD:
fio_ctr &= ~FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_SD;
break;
case SELECT_FIO_SDIO:
fio_ctr |= FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_SD;
break;
case SELECT_FIO_SD2:
#if (FIO_SUPPORT_AHB_CLK_ENA == 1)
fio_amb_cf_disable();
fio_amb_sd2_enable();
#endif
#if (CHIP_REV == A7L)
fio_ctr &= ~FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_SD;
#endif
break;
default:
break;
}
#if (SD_HAS_INTERNAL_MUXER == 1)
if (module != SELECT_FIO_SDIO) {
#if (HANDLE_SDIO_FAKE_IRQ == 1)
amba_clrbitsw(SD_NISEN_REG, SD_NISEN_CARD);
#endif
//SMIO_38 ~ SMIO_43
amba_clrbitsl(GPIO2_AFSEL_REG, 0x000007e0);
}
#endif
amba_writel(FIO_DMACTR_REG, fio_dmactr);
amba_writel(FIO_CTR_REG, fio_ctr);
#if (SD_HAS_INTERNAL_MUXER == 1)
if (module == SELECT_FIO_SDIO) {
//SMIO_38 ~ SMIO_43
amba_setbitsl(GPIO2_AFSEL_REG, 0x000007e0);
}
#endif
}
