void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* iomux and setup of i2c */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
/* Make sure we use dte mode */
setup_dtemode_uart();
#endif
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
void board_init_f(ulong dummy)
{
/* Set global data pointer */
gd = &gdata;
/* Linux expects the internal registers to be at 0xf1000000 */
arch_cpu_init();
/*
* Pin muxing needs to be done before UART output, since
* on A38x the UART pins need some re-muxing for output
* to work.
*/
board_early_init_f();
preloader_console_init();
timer_init();
/* First init the serdes PHY's */
serdes_phy_config();
/* Setup DDR */
ddr3_init();
board_init_r(NULL, 0);
}
static int x86_tpl_init(void)
{
int ret;
debug("%s starting\n", __func__);
ret = spl_init();
if (ret) {
debug("%s: spl_init() failed\n", __func__);
return ret;
}
ret = arch_cpu_init();
if (ret) {
debug("%s: arch_cpu_init() failed\n", __func__);
return ret;
}
ret = arch_cpu_init_dm();
if (ret) {
debug("%s: arch_cpu_init_dm() failed\n", __func__);
return ret;
}
preloader_console_init();
ret = print_cpuinfo();
if (ret) {
debug("%s: print_cpuinfo() failed\n", __func__);
return ret;
}
return 0;
}
void board_init_f(ulong dummy)
{
ccgr_init();
arch_cpu_init();
gpr_init();
/* setup GP timer */
timer_init();
displ5_set_iomux_uart_spl();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
displ5_init_ecspi();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
displ5_set_iomux_misc_spl();
/* Initialize and reset WDT in SPL */
hw_watchdog_init();
WATCHDOG_RESET();
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
int do_lowlevel_init(void)
{
uint32_t reset_status;
int actions = 0;
arch_cpu_init();
reset_status = get_reset_status();
switch (reset_status) {
case S5P_CHECK_SLEEP:
actions = DO_CLOCKS | DO_WAKEUP;
break;
case S5P_CHECK_DIDLE:
case S5P_CHECK_LPA:
actions = DO_WAKEUP;
break;
default:
/* This is a normal boot (not a wake from sleep) */
actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
}
if (actions & DO_POWER)
set_ps_hold_ctrl();
if (actions & DO_CLOCKS) {
//system_clock_init();
//mem_ctrl_init(actions & DO_MEM_RESET);
//tzpc_init();
}
return actions & DO_WAKEUP;
}
static void cpu_init(struct per_cpu *cpu_data)
{
int err = -EINVAL;
printk(" CPU %d... ", cpu_data->cpu_id);
if (!cpu_id_valid(cpu_data->cpu_id))
goto failed;
cpu_data->cell = &root_cell;
err = arch_cpu_init(cpu_data);
if (err)
goto failed;
printk("OK\n");
/*
* If this CPU is last, make sure everything was committed before we
* signal the other CPUs spinning on initialized_cpus that they can
* continue.
*/
memory_barrier();
initialized_cpus++;
return;
failed:
printk("FAILED\n");
if (!error)
error = err;
}
void board_init_f(ulong dummy)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/*
* We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
* initializes DMA very early (before all board code), so the only
* opportunity we have to initialize APBHDMA clocks is in SPL.
*/
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
enable_usdhc_clk(1, 2);
arch_cpu_init();
timer_init();
cm_fx6_setup_ecspi();
cm_fx6_setup_uart();
get_clocks();
preloader_console_init();
gpio_direction_output(CM_FX6_GREEN_LED, 1);
if (cm_fx6_spl_dram_init()) {
puts("!!!ERROR!!! DRAM detection failed!!!\n");
hang();
}
memset(__bss_start, 0, __bss_end - __bss_start);
board_init_r(NULL, 0);
}
void board_init_f(ulong dummy)
{
ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* iomux and setup of i2c */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
void board_init_f(ulong dummy)
{
/* Set global data pointer */
gd = &gdata;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
#ifdef CONFIG_LS2085A
arch_cpu_init();
#endif
#ifdef CONFIG_FSL_IFC
init_early_memctl_regs();
#endif
board_early_init_f();
timer_init();
#ifdef CONFIG_LS2085A
env_init();
#endif
get_clocks();
preloader_console_init();
#ifdef CONFIG_SPL_I2C_SUPPORT
i2c_init_all();
#endif
dram_init();
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
board_init_r(NULL, 0);
}
void board_init_f(ulong dummy)
{
#ifdef CONFIG_CMD_NAND
/* Enable NAND */
setup_gpmi_nand();
#endif
/* setup clock gating */
ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* setup AXI */
gpr_init();
board_early_init_f();
/* setup GP timer */
timer_init();
setup_spi();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
INITCODE void arch_processor_init(cpu_id_t cpuid)
{
arch_cpu_init(cpuid);
if (cpu_has_feature(X86_FTR_APIC)) {
lapic_init(cpuid);
lapic_timer_init(cpuid);
}
}
/*
* This section requires the differentiation between iMX6 Sabre boards, but
* for now, it will configure only for the mx6q variant.
*/
static void spl_dram_init(void)
{
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = 2,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
/* single chip select */
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 7, /* 8 refresh commands per refresh cycle */
};
if (is_mx6dqp()) {
mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr);
} else {
mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
}
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* iomux and setup of i2c */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
void spl_board_init(void)
{
#ifdef CONFIG_SOC_DM365
dm36x_lowlevel_init(0);
#endif
#ifdef CONFIG_SOC_DA8XX
arch_cpu_init();
#endif
preloader_console_init();
}
void board_init_f(ulong dummy)
{
ps7_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
preloader_console_init();
arch_cpu_init();
board_init_r(NULL, 0);
}
void board_init_f(ulong dummy)
{
ps7_init();
arch_cpu_init();
/*
* The debug UART can be used from this point:
* debug_uart_init();
* printch('x');
*/
}
void board_init_f(ulong dummy)
{
arch_cpu_init();
gpr_init();
board_early_init_f();
timer_init();
preloader_console_init();
ddr_init();
memset(__bss_start, 0, __bss_end - __bss_start);
board_init_r(NULL, 0);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
bd_t *bd;
memset(gd, 0, sizeof(gd_t));
bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
bd->bi_memsize = CONFIG_SYS_L2_SIZE;
arch_cpu_init();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
#endif
/* relocate environment function pointers etc. */
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = ENV_VALID;
#else
env_relocate();
#endif
i2c_init_all();
dram_init();
#ifdef CONFIG_SPL_NAND_BOOT
puts("\nTertiary program loader running in sram...");
#else
puts("\nSecond program loader running in sram...");
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
fsl_spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
}
void board_init_f(ulong dummy)
{
ps7_init();
arch_cpu_init();
#ifdef CONFIG_DEBUG_UART
/* Uart debug for sure */
debug_uart_init();
puts("Debug uart enabled\n"); /* or printch() */
#endif
}
void board_init_f(ulong dummy)
{
#if 0
arch_cpu_init();
board_early_init_f();
timer_init();
preloader_console_init();
print_cpuinfo();
board_init_r(NULL, 0);
#endif
}
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
* - no variable global data is available
*/
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* setup GP timer */
timer_init();
#ifdef CONFIG_BOARD_POSTCLK_INIT
board_postclk_init();
#endif
#ifdef CONFIG_FSL_ESDHC
get_clocks();
#endif
/* Setup IOMUX and configure basics. */
novena_spl_setup_iomux_audio();
novena_spl_setup_iomux_buttons();
novena_spl_setup_iomux_enet();
novena_spl_setup_iomux_fpga();
novena_spl_setup_iomux_i2c();
novena_spl_setup_iomux_pcie();
novena_spl_setup_iomux_sdhc();
novena_spl_setup_iomux_spi();
novena_spl_setup_iomux_uart();
novena_spl_setup_iomux_video();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* Start the DDR DRAM */
novena_read_spd(&novena_ddr_info, &novena_ddr3_cfg);
mx6dq_dram_iocfg(novena_ddr3_cfg.width,
&novena_ddr_ioregs, &novena_grp_ioregs);
mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &novena_ddr3_cfg);
do_write_level_calibration();
do_dqs_calibration();
printf("Running post-config memory test... ");
if (novena_memory_test())
printf("Fail!\n");
else
printf("Pass\n");
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
void board_init_f(ulong dummy)
{
ps7_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* Set global data pointer. */
gd = &gdata;
preloader_console_init();
arch_cpu_init();
board_init_r(NULL, 0);
}
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
* - no variable global data is available
*/
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* setup GP timer */
timer_init();
#ifdef CONFIG_BOARD_POSTCLK_INIT
board_postclk_init();
#endif
#ifdef CONFIG_FSL_ESDHC
get_clocks();
#endif
/* Setup IOMUX and configure basics. */
novena_spl_setup_iomux_audio();
novena_spl_setup_iomux_buttons();
novena_spl_setup_iomux_enet();
novena_spl_setup_iomux_fpga();
novena_spl_setup_iomux_i2c();
novena_spl_setup_iomux_pcie();
novena_spl_setup_iomux_sdhc();
novena_spl_setup_iomux_spi();
novena_spl_setup_iomux_uart();
novena_spl_setup_iomux_video();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* Start the DDR DRAM */
mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600);
/* Perform DDR DRAM calibration */
udelay(100);
mmdc_do_write_level_calibration();
mmdc_do_dqs_calibration();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
void board_init_f(ulong dummy)
{
ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
gpr_init();
/* iomux */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
arch_cpu_init();
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) {
debug("Clock init failed: %d\n", ret);
return;
}
ret = uclass_get_device(UCLASS_RESET, 0, &dev);
if (ret) {
debug("Reset init failed: %d\n", ret);
return;
}
ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev);
if (ret) {
debug("%s: Cannot find pinctrl device\n", __func__);
return;
}
/* enable console uart printing */
preloader_console_init();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
debug("DRAM init failed: %d\n", ret);
return;
}
}
void board_init_f(ulong dummy)
{
ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
if (!(is_mx6ul()))
gpr_init();
/* iomux */
SETUP_IOMUX_PADS(uart_pads);
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
}
void board_init_f(ulong dummy)
{
int ret;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
arch_cpu_init();
init_uart_clk(0);
board_early_init_f();
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
enable_tzc380();
/* Adjust pmic voltage to 1.0V for 800M */
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
power_init_board();
/* DDR initialization */
spl_dram_init();
board_init_r(NULL, 0);
}
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* setup GP timer */
timer_init();
setup_iomux_boardid();
setup_iomux_gpio();
setup_iomux_enet();
setup_iomux_sd();
setup_iomux_spi();
setup_iomux_uart();
setup_iomux_usb();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* Start the DDR DRAM */
if (is_mx6dq())
mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs,
&dhcom6dq_grp_ioregs);
else
mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs,
&dhcom6sdl_grp_ioregs);
mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
bd_t *bd;
memset(gd, 0, sizeof(gd_t));
bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
bd->bi_memsize = CONFIG_SYS_L2_SIZE;
arch_cpu_init();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
/* relocate environment function pointers etc. */
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = ENV_VALID;
i2c_init_all();
dram_init();
#ifdef CONFIG_SPL_NAND_BOOT
puts("TPL\n");
#else
puts("SPL\n");
#endif
nand_boot();
}
void board_init_f(ulong dummy)
{
unsigned int ramchip;
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = 2,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 512 MB */
/* single chip select */
#if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
.ncs = 1,
#else
.ncs = 2,
#endif
.cs1_mirror = 1,
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 7, /* 8 refresh commands per refresh cycle */
};
#ifdef CONFIG_CMD_NAND
/* Enable NAND */
setup_gpmi_nand();
#endif
/* setup clock gating */
ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* setup AXI */
gpr_init();
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
setup_spi();
setup_gpios();
/* DDR initialization */
spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]);
ramchip = pfla02_detect_chiptype();
debug("Detected chip %d\n", ramchip);
#if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
switch (ramchip) {
case RAM_MT64K:
sysinfo.cs_density = 6;
break;
case RAM_MT128K:
sysinfo.cs_density = 10;
break;
case RAM_MT256K:
sysinfo.cs_density = 18;
break;
}
#endif
spl_dram_init(&sysinfo, &mt41k_xx[ramchip]);
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
phyflex_err006282_workaround();
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
static void spl_dram_init(int width)
{
struct mx6_ddr3_cfg *mem = &mt41k256m16ha_125;
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = width / 32,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
/* single chip select */
.ncs = 1,
.cs1_mirror = 1,
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
#ifdef RTT_NOM_120OHM
.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
#else
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
#endif
.walat = 0, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 7, /* 8 refresh commands per refresh cycle */
};
mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem);
}
/*
* Called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
* - no variable global data is available
*/
void board_init_f(ulong dummy)
{
/* Setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* UART iomux */
board_early_init_f();
/* Setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* Init DDR with 32bit width */
spl_dram_init(32);
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
/*
* Setup enet related MUXing early to give the PHY
* some time to wake-up from reset
*/
platinum_setup_enet();
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
