void arch_idle(void)
{
if (enable_wait_mode) {
mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
if (mem_clk_on_in_wait) {
u32 reg;
/*
* MX6SL, MX6Q (TO1.2 or later) and
* MX6DL (TO1.1 or later) have a bit in CCM_CGPR that
* when cleared keeps the clocks to memories ON
* when ARM is in WFI. This mode can be used when
* IPG clock is very low (12MHz) and the ARM:IPG ratio
* perhaps cannot be maintained.
*/
reg = __raw_readl(MXC_CCM_CGPR);
reg &= ~MXC_CCM_CGPR_MEM_IPG_STOP_MASK;
__raw_writel(reg, MXC_CCM_CGPR);
ca9_do_idle();
} else if (num_possible_cpus() == 1)
/* iMX6SL or iMX6DLS */
arch_idle_single_core();
else
arch_idle_multi_core();
} else {
mxc_cpu_lp_set(WAIT_CLOCKED);
ca9_do_idle();
}
}
void arch_idle(void)
{
int cpu = smp_processor_id();
if (enable_wait_mode) {
#ifdef CONFIG_LOCAL_TIMERS
if (!tick_broadcast_oneshot_active()
|| !tick_oneshot_mode_active())
return;
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
#endif
if (enet_is_active)
/* Don't allow the chip to enter WAIT mode if enet is active
* and the GPIO workaround for ENET interrupts is not used,
* since all ENET interrupts donot wake up the SOC.
*/
mxc_cpu_lp_set(WAIT_CLOCKED);
else
mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
if (mem_clk_on_in_wait) {
u32 reg;
/*
* MX6SL, MX6Q (TO1.2 or later) and
* MX6DL (TO1.1 or later) have a bit in
* CCM_CGPR that when cleared keeps the
* clocks to memories ON when ARM is in WFI.
* This mode can be used when IPG clock is
* very low (12MHz) and the ARM:IPG ratio
* perhaps cannot be maintained.
*/
reg = __raw_readl(MXC_CCM_CGPR);
reg &= ~MXC_CCM_CGPR_MEM_IPG_STOP_MASK;
__raw_writel(reg, MXC_CCM_CGPR);
ca9_do_idle();
} else if (num_possible_cpus() == 1)
/* iMX6SL or iMX6DLS */
arch_idle_single_core();
else
arch_idle_multi_core(cpu);
#ifdef CONFIG_LOCAL_TIMERS
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
#endif
} else {
mxc_cpu_lp_set(WAIT_CLOCKED);
ca9_do_idle();
}
}
