static __devinit int acx00_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct acx00 *acx00;
#ifndef AUDIO_RSB_BUS
int ret = 0;
#endif
pr_err("%s, line:%d, i2c->irq:%d\n", __func__, __LINE__, i2c->irq);
acx00 = devm_kzalloc(&i2c->dev, sizeof(struct acx00), GFP_KERNEL);
if (acx00 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, acx00);
acx00->dev = &i2c->dev;
acx00->irq = i2c->irq;
mutex_init(&acx00->lock);
#ifdef AUDIO_RSB_BUS
if (arisc_rsb_set_rtsaddr(RSB_DEVICE_SADDR7, RSB_RTSADDR_ACX00)) {
pr_err("AUDIO config codec failed\n");
}
#else
acx00->regmap = devm_regmap_init_i2c(i2c, &acx00_base_regmap_config);
if (IS_ERR(acx00->regmap)) {
ret = PTR_ERR(acx00->regmap);
dev_err(acx00->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
acx00->pwm_ac200 = pwm_request(0, NULL);
pwm_config(acx00->pwm_ac200, 20, 41);
pwm_enable(acx00->pwm_ac200);
acx00_reg_write(acx00, 0x0002,0x1);
#endif
return acx00_device_init(acx00, i2c->irq);
}
static int __init sunxi_init_ac100_clocks(void)
{
struct clk *clk;
struct clk *parent;
int i;
struct periph_init_data *periph;
if (arisc_rsb_set_rtsaddr(RSB_DEVICE_SADDR7, RSB_RTSADDR_AC100)) {
pr_err("%s err: config codec failed\n", __func__);
return -1;
}
//reigster source for AC100 32K
clk = clk_register_fixed_rate(NULL, "32k_rtc", NULL, CLK_IS_ROOT, 32768);
clk_register_clkdev(clk, "32k_rtc", NULL);
clk = clk_register_fixed_rate(NULL, "4m_adda", NULL, CLK_IS_ROOT, 4000000);
clk_register_clkdev(clk, "4m_adda", NULL);
sunxi_clk_get_periph_ops(&ac100_clkops);
ac100_clkops.prepare = ac100_clkops.enable;
ac100_clkops.unprepare = ac100_clkops.disable;
ac100_clkops.enable = NULL;
ac100_clkops.disable = NULL;
ac100_clkops.recalc_rate = sunxi_ac100_recalc_rate;
ac100_clkops.round_rate = sunxi_ac100_round_rate;
ac100_clkops.set_rate = __sunxi_clk_periph_set_rate;
ac100_regops.reg_writel = ac100_writel;
ac100_regops.reg_readl = ac100_readl;
/* register AC100 clock */
for(i=0; i<ARRAY_SIZE(sunxi_ac100_init); i++)
{
periph = &sunxi_ac100_init[i];
periph->periph->priv_clkops = &ac100_clkops;
periph->periph->priv_regops = &ac100_regops;
clk = sunxi_clk_register_periph(periph->name, periph->parent_names,
periph->num_parents,periph->flags, NULL, periph->periph);
clk_register_clkdev(clk, periph->name, NULL);
}
//Sync enable count for Ac100
for(i=0; i<ARRAY_SIZE(sunxi_ac100_init); i++)
{
periph = &sunxi_ac100_init[i];
clk = clk_get(NULL,periph->name);
if(!clk || IS_ERR(clk))
continue;
if((!clk->prepare_count) && (!clk->enable_count) && clk->ops->is_enabled(clk->hw))
{
clk->prepare_count++;
clk->enable_count++;
parent = clk->parent;
while(parent)
{
parent->enable_count++;
parent->prepare_count++;
parent = parent->parent;
}
}
clk_put(clk);
}
return 0;
}
