void bl2_platform_setup(void)
{
arm_bl2_platform_setup();
mmio_write_32(SCP_BOOT_CFG_ADDR, scp_boot_config);
VERBOSE("BL2: Restored SCP Boot config = 0x%x\n", scp_boot_config);
}
void bl2_platform_setup(void)
{
arm_bl2_platform_setup();
/*
* Before releasing the AP cores out of reset, the SCP writes some data
* at the beginning of the Trusted SRAM. It is is overwritten before
* reaching this function. We need to restore this data, as if the
* target had just come out of reset. This implies:
* - zeroing the first 128 bytes of Trusted SRAM;
* - restoring the SCP boot configuration.
*/
VERBOSE("BL2: Restoring SCP reset data in Trusted SRAM\n");
memset((void *) ARM_TRUSTED_SRAM_BASE, 0, 128);
mmio_write_32(SCP_BOOT_CFG_ADDR, scp_boot_config);
}
void bl2_platform_setup(void)
{
arm_bl2_platform_setup();
#ifdef FVP_VE_USE_SP804_TIMER
/*
* Enable the clock override for SP804 timer 0, which means that no
* clock dividers are applied and the raw (35 MHz) clock will be used
*/
mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
/* Initialize delay timer driver using SP804 dual timer 0 */
sp804_timer_init(V2M_SP804_TIMER0_BASE,
SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
#else
generic_delay_timer_init();
#endif /* FVP_VE_USE_SP804_TIMER */
}
void bl2_platform_setup(void)
{
arm_bl2_platform_setup();
}
