Exemplo n.º 1
0
static int __init merisc_init(void)
{
    detect_merisc_board_id();

    printk(KERN_NOTICE "BOARD: Merisc %s revision %s\n", merisc_model(),
           merisc_revision());

    /* Reserve pins for SDRAM */
    at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL | (1 << 26));

    if (merisc_board_id >= 1)
        at32_map_usart(2, 2, 0);

    at32_add_device_usart(0);
    at32_add_device_usart(1);
    if (merisc_board_id >= 1)
        at32_add_device_usart(2);
    at32_add_device_usart(3);
    set_hw_addr(at32_add_device_eth(0, &eth_data[0]));

    /* ADS7846 PENIRQ */
    if (merisc_board_id == 0) {
        ads7846_data.get_pendown_state = ads7846_get_pendown_state_PB26;
        at32_select_periph(GPIO_PIOB_BASE, 1 << 26,
                           GPIO_PERIPH_A, AT32_GPIOF_PULLUP);
        spi0_board_info[0].irq = AT32_EXTINT(1);
    } else {
        ads7846_data.get_pendown_state = ads7846_get_pendown_state_PB28;
        at32_select_periph(GPIO_PIOB_BASE, 1 << 28, GPIO_PERIPH_A,
                           AT32_GPIOF_PULLUP);
        spi0_board_info[0].irq = AT32_EXTINT(3);
    }

    /* ADS7846 busy pin */
    at32_select_gpio(GPIO_PIN_PA(4), AT32_GPIOF_PULLUP);

    at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));

    at32_add_device_mci(0, &mci0_data);

#ifdef CONFIG_LEDS_ATMEL_PWM
    at32_add_device_pwm((1 << 0) | (1 << 2));
    platform_device_register(&stk_pwm_led_dev);
#else
    at32_add_device_pwm((1 << 2));
#endif

    at32_select_gpio(i2c_gpio_data.sda_pin,
                     AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
    at32_select_gpio(i2c_gpio_data.scl_pin,
                     AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
    platform_device_register(&i2c_gpio_device);

    i2c_register_board_info(0, i2c_info, ARRAY_SIZE(i2c_info));

    return 0;
}
static void __init atstk1004_setup_extdac(void)
{
	struct clk *gclk;
	struct clk *pll;

	gclk = clk_get(NULL, "gclk0");
	if (IS_ERR(gclk))
		goto err_gclk;
	pll = clk_get(NULL, "pll0");
	if (IS_ERR(pll))
		goto err_pll;

	if (clk_set_parent(gclk, pll)) {
		pr_debug("STK1000: failed to set pll0 as parent for DAC clock\n");
		goto err_set_clk;
	}

	at32_select_periph(GPIO_PIOA_BASE, (1 << 30), GPIO_PERIPH_A, 0);
	at73c213_data.dac_clk = gclk;

err_set_clk:
	clk_put(pll);
err_pll:
	clk_put(gclk);
err_gclk:
	return;
}
Exemplo n.º 3
0
static int __init at32_init_ide_or_cf(struct platform_device *pdev,
		unsigned int cs, unsigned int extint)
{
	static unsigned int extint_pin_map[4] __initdata = {
		GPIO_PIN_PB(25),
		GPIO_PIN_PB(26),
		GPIO_PIN_PB(27),
		GPIO_PIN_PB(28),
	};
	static bool common_pins_initialized __initdata = false;
	unsigned int extint_pin;
	int ret;

	if (extint >= ARRAY_SIZE(extint_pin_map))
		return -EINVAL;
	extint_pin = extint_pin_map[extint];

	switch (cs) {
	case 4:
		ret = platform_device_add_resources(pdev,
				at32_smc_cs4_resource,
				ARRAY_SIZE(at32_smc_cs4_resource));
		if (ret)
			return ret;

		select_peripheral(PE(21), PERIPH_A, 0); /* NCS4   -> OE_N  */
		set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
		break;
	case 5:
		ret = platform_device_add_resources(pdev,
				at32_smc_cs5_resource,
				ARRAY_SIZE(at32_smc_cs5_resource));
		if (ret)
			return ret;

		select_peripheral(PE(22), PERIPH_A, 0); /* NCS5   -> OE_N  */
		set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
		break;
	default:
		return -EINVAL;
	}

	if (!common_pins_initialized) {
		select_peripheral(PE(19), PERIPH_A, 0);	/* CFCE1  -> CS0_N */
		select_peripheral(PE(20), PERIPH_A, 0);	/* CFCE2  -> CS1_N */
		select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW  -> DIR   */
		select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT  <- IORDY */
		common_pins_initialized = true;
	}

	at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);

	pdev->resource[1].start = EIM_IRQ_BASE + extint;
	pdev->resource[1].end = pdev->resource[1].start;

	return 0;
}
Exemplo n.º 4
0
static int __init hammerhead_init(void)
{
	/*
	 * Hammerhead uses 32-bit SDRAM interface. Reserve the
	 * SDRAM-specific pins so that nobody messes with them.
	 */
	at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL);

	at32_add_device_usart(0);

	/* Reserve PB29 (GCLK3). This pin is used as clock source
	 * for ETH PHY (25MHz). GCLK3 setup is done by U-Boot.
	 */
	at32_reserve_pin(GPIO_PIOB_BASE, (1<<29));

	/*
	 * Hammerhead uses only one ethernet port, so we don't set
	 * address of second port
	 */
	set_hw_addr(at32_add_device_eth(0, &eth_data[0]));

#ifdef CONFIG_BOARD_HAMMERHEAD_FPGA
	at32_add_device_hh_fpga();
#endif
	at32_add_device_mci(0, &mci0_data);

#ifdef CONFIG_BOARD_HAMMERHEAD_USB
	at32_add_device_usba(0, NULL);
#endif
#ifdef CONFIG_BOARD_HAMMERHEAD_LCD
	at32_add_device_lcdc(0, &hammerhead_lcdc_data, fbmem_start,
			     fbmem_size, ATMEL_LCDC_PRI_24BIT);
#endif

	at32_select_gpio(i2c_gpio_data.sda_pin,
			 AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT |
			 AT32_GPIOF_HIGH);
	at32_select_gpio(i2c_gpio_data.scl_pin,
			 AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT |
			 AT32_GPIOF_HIGH);
	platform_device_register(&i2c_gpio_device);
	i2c_register_board_info(0, i2c_info, ARRAY_SIZE(i2c_info));

#ifdef CONFIG_BOARD_HAMMERHEAD_SND
	at32_add_device_ac97c(0, &ac97c_data, AC97C_BOTH);
#endif

	/* Select the Touchscreen interrupt pin mode */
	at32_select_periph(GPIO_PIOB_BASE, 0x08000000, GPIO_PERIPH_A, 0);

	return 0;
}
Exemplo n.º 5
0
struct platform_device *__init at32_add_device_hh_fpga(void)
{
	/* Select peripheral functionallity for SPI SCK and MOSI */
	at32_select_periph(GPIO_PIOB_BASE, HAMMERHEAD_FPGA_PERIPH_SCK,
			   GPIO_PERIPH_B, 0);
	at32_select_periph(GPIO_PIOB_BASE, HAMMERHEAD_FPGA_PERIPH_MOSI,
			   GPIO_PERIPH_B, 0);

	/* reserve all other needed gpio
	 * We have on board pull ups, so there is no need
	 * to enable gpio pull ups */
	/* INIT_DONE (input) */
	at32_select_gpio(GPIO_PIN_PB(0), 0);

	/* nSTATUS (input) */
	at32_select_gpio(GPIO_PIN_PB(2), 0);

	/* nCONFIG (output, low) */
	at32_select_gpio(GPIO_PIN_PB(3), AT32_GPIOF_OUTPUT);

	/* CONF_DONE (input) */
	at32_select_gpio(GPIO_PIN_PB(4), 0);

	/* Select EXTINT3 for PB28 (Interrupt from FPGA) */
	at32_select_periph(GPIO_PIOB_BASE, HAMMERHEAD_FPGA_PERIPH_EXTINT3,
			   GPIO_PERIPH_A, 0);

	/* Get our parent clock */
	hh_fpga0_spi_clk.parent = clk_get(NULL, "pba");
	clk_put(hh_fpga0_spi_clk.parent);

	/* Register clock in at32 clock tree */
	at32_clk_register(&hh_fpga0_spi_clk);

	platform_device_register(&hh_fpga0_device);
	return &hh_fpga0_device;
}
static int __init playpaq_asoc_init(void)
{
	int ret = 0;

	/*
	 * Configure MCLK for WM8510
	 */
	_gclk0 = clk_get(NULL, "gclk0");
	if (IS_ERR(_gclk0)) {
		_gclk0 = NULL;
		goto err_gclk0;
	}
	_pll0 = clk_get(NULL, "pll0");
	if (IS_ERR(_pll0)) {
		_pll0 = NULL;
		goto err_pll0;
	}
	if (clk_set_parent(_gclk0, _pll0)) {
		pr_warning("snd-soc-playpaq: "
			   "Failed to set PLL0 as parent for DAC clock\n");
		goto err_set_clk;
	}
	clk_set_rate(CODEC_CLK, 12000000);
	clk_enable(CODEC_CLK);

#if defined CONFIG_AT32_ENHANCED_PORTMUX
	at32_select_periph(MCLK_PIN, MCLK_PERIPH, 0);
#endif


	/*
	 * Create and register platform device
	 */
	playpaq_snd_device = platform_device_alloc("soc-audio", 0);
	if (playpaq_snd_device == NULL) {
		ret = -ENOMEM;
		goto err_device_alloc;
	}

	platform_set_drvdata(playpaq_snd_device, &snd_soc_playpaq);

	ret = platform_device_add(playpaq_snd_device);
	if (ret) {
		pr_warning("playpaq_wm8510: platform_device_add failed (%d)\n",
			   ret);
		goto err_device_add;
	}

	return 0;


err_device_add:
	if (playpaq_snd_device != NULL) {
		platform_device_put(playpaq_snd_device);
		playpaq_snd_device = NULL;
	}
err_device_alloc:
err_set_clk:
	if (_pll0 != NULL) {
		clk_put(_pll0);
		_pll0 = NULL;
	}
err_pll0:
	if (_gclk0 != NULL) {
		clk_put(_gclk0);
		_gclk0 = NULL;
	}
	return ret;
}
Exemplo n.º 7
0
static int __init playpaq_asoc_init(void)
{
	int ret = 0;
	struct at32_ssc_info *ssc_p = playpaq_wm8510_dai.cpu_dai->private_data;
	struct ssc_device *ssc = NULL;


	/*
	 * Request SSC device
	 */
	ssc = ssc_request(0);
	if (IS_ERR(ssc)) {
		ret = PTR_ERR(ssc);
		ssc = NULL;
		goto err_ssc;
	}
	ssc_p->ssc = ssc;


	/*
	 * Configure MCLK for WM8510
	 */
	_gclk0 = clk_get(NULL, "gclk0");
	if (IS_ERR(_gclk0)) {
		_gclk0 = NULL;
		goto err_gclk0;
	}
	_pll0 = clk_get(NULL, "pll0");
	if (IS_ERR(_pll0)) {
		_pll0 = NULL;
		goto err_pll0;
	}
	if (clk_set_parent(_gclk0, _pll0)) {
		pr_warning("snd-soc-playpaq: "
			   "Failed to set PLL0 as parent for DAC clock\n");
		goto err_set_clk;
	}
	clk_set_rate(CODEC_CLK, 12000000);
	clk_enable(CODEC_CLK);

#if defined CONFIG_AT32_ENHANCED_PORTMUX
	at32_select_periph(MCLK_PIN, MCLK_PERIPH, 0);
#endif


	/*
	 * Create and register platform device
	 */
	playpaq_snd_device = platform_device_alloc("soc-audio", 0);
	if (playpaq_snd_device == NULL) {
		ret = -ENOMEM;
		goto err_device_alloc;
	}

	platform_set_drvdata(playpaq_snd_device, &playpaq_wm8510_snd_devdata);
	playpaq_wm8510_snd_devdata.dev = &playpaq_snd_device->dev;

	ret = platform_device_add(playpaq_snd_device);
	if (ret) {
		pr_warning("playpaq_wm8510: platform_device_add failed (%d)\n",
			   ret);
		goto err_device_add;
	}

	return 0;


err_device_add:
	if (playpaq_snd_device != NULL) {
		platform_device_put(playpaq_snd_device);
		playpaq_snd_device = NULL;
	}
err_device_alloc:
err_set_clk:
	if (_pll0 != NULL) {
		clk_put(_pll0);
		_pll0 = NULL;
	}
err_pll0:
	if (_gclk0 != NULL) {
		clk_put(_gclk0);
		_gclk0 = NULL;
	}
err_gclk0:
	if (ssc != NULL) {
		ssc_free(ssc);
		ssc = NULL;
	}
err_ssc:
	return ret;
}
Exemplo n.º 8
0
static int __init mrmt1_init(void)
{
	gpio_set_value( PIN_PWR_ON, 1 );	/* Ensure PWR_ON is enabled */

	pm_power_off = mrmt_power_off;

	/* Setup USARTS (other than console) */
	at32_map_usart(2, 1, 0);	/* USART 2: /dev/ttyS1, RMT1:DB9M */
	at32_map_usart(3, 2, ATMEL_USART_RTS | ATMEL_USART_CTS);
			/* USART 3: /dev/ttyS2, RMT1:Wireless, w/ RTS/CTS */
	at32_add_device_usart(1);
	at32_add_device_usart(2);

	/* Select GPIO Key pins */
	at32_select_gpio( PIN_PWR_SW_N, AT32_GPIOF_DEGLITCH);
	at32_select_gpio( PIN_PB_LEFT, AT32_GPIOF_DEGLITCH);
	at32_select_gpio( PIN_PB_RIGHT, AT32_GPIOF_DEGLITCH);
	platform_device_register(&rmt_gpio_keys);

#ifdef CONFIG_BOARD_MRMT_RTC_I2C
	i2c_register_board_info(0, &mrmt1_i2c_rtc, 1);
#endif

#ifndef CONFIG_BOARD_MRMT_LCD_DISABLE
	/* User "alternate" LCDC inferface on Port E & D */
	/* NB: exclude LCDC_CC pin, as NGW100 reserves it for other use */
	at32_add_device_lcdc(0, &rmt_lcdc_data,
		fbmem_start, fbmem_size,
		(ATMEL_LCDC_ALT_24BIT | ATMEL_LCDC_PE_DVAL ) );
#endif

#ifdef CONFIG_BOARD_MRMT_AC97
	at32_add_device_ac97c(0, &ac97c0_data, AC97C_BOTH);
#endif

#ifdef CONFIG_BOARD_MRMT_ADS7846_TS
	/* Select the Touchscreen interrupt pin mode */
	at32_select_periph( GPIO_PIOB_BASE, 1 << (PB_EXTINT_BASE+TS_IRQ),
			GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
	irq_set_irq_type(AT32_EXTINT(TS_IRQ), IRQ_TYPE_EDGE_FALLING);
	at32_spi_setup_slaves(0,spi01_board_info,ARRAY_SIZE(spi01_board_info));
	spi_register_board_info(spi01_board_info,ARRAY_SIZE(spi01_board_info));
#endif

#ifdef CONFIG_BOARD_MRMT_UCB1400_TS
	/* Select the Touchscreen interrupt pin mode */
	at32_select_periph( GPIO_PIOB_BASE, 1 << (PB_EXTINT_BASE+TS_IRQ),
			GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
	platform_device_register(&rmt_ts_device);
#endif

	at32_select_gpio( PIN_LCD_DISP, AT32_GPIOF_OUTPUT );
	gpio_request( PIN_LCD_DISP, "LCD_DISP" );
	gpio_direction_output( PIN_LCD_DISP, 0 );	/* LCD DISP */
#ifdef CONFIG_BOARD_MRMT_LCD_DISABLE
	/* Keep Backlight and DISP off */
	at32_select_gpio( PIN_LCD_BL, AT32_GPIOF_OUTPUT );
	gpio_request( PIN_LCD_BL, "LCD_BL" );
	gpio_direction_output( PIN_LCD_BL, 0 );		/* Backlight */
#else
	gpio_set_value( PIN_LCD_DISP, 1 );	/* DISP asserted first */
#ifdef CONFIG_BOARD_MRMT_BL_PWM
	/* Use PWM for Backlight controls */
	at32_add_device_pwm(1 << PWM_CH_BL);
	platform_device_register(&rmt_pwm_led_dev);
#else
	/* Backlight always on */
	udelay( 1 );
	at32_select_gpio( PIN_LCD_BL, AT32_GPIOF_OUTPUT );
	gpio_request( PIN_LCD_BL, "LCD_BL" );
	gpio_direction_output( PIN_LCD_BL, 1 );
#endif
#endif

	/* Make sure BT and Zigbee modules in reset */
	at32_select_gpio( PIN_BT_RST, AT32_GPIOF_OUTPUT );
	gpio_request( PIN_BT_RST, "BT_RST" );
	gpio_direction_output( PIN_BT_RST, 1 );
	/* BT Module in Reset */

	at32_select_gpio( PIN_ZB_RST_N, AT32_GPIOF_OUTPUT );
	gpio_request( PIN_ZB_RST_N, "ZB_RST_N" );
	gpio_direction_output( PIN_ZB_RST_N, 0 );
	/* XBee Module in Reset */

#ifdef CONFIG_BOARD_MRMT_WIRELESS_ZB
	udelay( 1000 );
	/* Unreset the XBee Module */
	gpio_set_value( PIN_ZB_RST_N, 1 );
#endif
#ifdef CONFIG_BOARD_MRMT_WIRELESS_BT
	udelay( 1000 );
	/* Unreset the BT Module */
	gpio_set_value( PIN_BT_RST, 0 );
#endif

	return 0;
}
Exemplo n.º 9
0
static int __init hammerhead_usbh_init(void)
{
	struct clk *gclk;
	struct clk *osc;

	int ret;

	/* setup smc for usbh */
	smc_set_timing(&isp1160_config, &isp1160_timing);
	ret = smc_set_configuration(2, &isp1160_config);

	if (ret < 0) {
		printk(KERN_ERR
		       "hammerhead: failed to set ISP1160 USBH timing\n");
		return ret;
	}

	/* setup gclk0 to run from osc1 */
	gclk = clk_get(NULL, "gclk0");
	if (IS_ERR(gclk)) {
		ret = PTR_ERR(gclk);
		goto err_gclk;
	}

	osc = clk_get(NULL, "osc1");
	if (IS_ERR(osc)) {
		ret = PTR_ERR(osc);
		goto err_osc;
	}

	ret = clk_set_parent(gclk, osc);
	if (ret < 0) {
		pr_debug("hammerhead: failed to set osc1 for USBH clock\n");
		goto err_set_clk;
	}

	/* set clock to 6MHz */
	clk_set_rate(gclk, 6000000);

	/* and enable */
	clk_enable(gclk);

	/* select GCLK0 peripheral function */
	at32_select_periph(GPIO_PIOA_BASE, HAMMERHEAD_USB_PERIPH_GCLK0,
			   GPIO_PERIPH_A, 0);

	/* enable CS2 peripheral function */
	at32_select_periph(GPIO_PIOE_BASE, HAMMERHEAD_USB_PERIPH_CS2,
			   GPIO_PERIPH_A, 0);

	/* H_WAKEUP must be driven low */
	at32_select_gpio(GPIO_PIN_PA(8), AT32_GPIOF_OUTPUT);

	/* Select EXTINT0 for PB25 */
	at32_select_periph(GPIO_PIOB_BASE, HAMMERHEAD_USB_PERIPH_EXTINT0,
			   GPIO_PERIPH_A, 0);

	/* register usbh device driver */
	platform_device_register(&isp1160_device);

 err_set_clk:
	clk_put(osc);
 err_osc:
	clk_put(gclk);
 err_gclk:
	return ret;
}