static void __init at91sam9261_map_io(void) { if (cpu_is_at91sam9g10()) at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE); else at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE); }
static void __init at91sam9260_map_io(void) { if (cpu_is_at91sam9xe()) at91sam9xe_map_io(); else if (cpu_is_at91sam9g20()) at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE); else at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE); }
static void __init at91sam9260_map_io(void) { if (cpu_is_at91sam9xe()) { at91sam9xe_map_io(); } else if (cpu_is_at91sam9g20()) { at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE); at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE); } else { at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE); at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE); } }
static void __init at91sam9260_map_io(void) { if (cpu_is_at91sam9xe()) { at91sam9xe_map_io(); } else if (cpu_is_at91sam9g20()) { at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE); at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE); } else { at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE); at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE); } #ifdef CONFIG_IPIPE iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc)); #endif /* CONFIG_IPIPE */ }
static void __init at91sam9xe_map_io(void) { unsigned long sram_size; switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) { case AT91_CIDR_SRAMSIZ_32K: sram_size = 2 * SZ_16K; break; case AT91_CIDR_SRAMSIZ_16K: default: sram_size = SZ_16K; } at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size); }
static void __init at91sam9x5_map_io(void) { at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE); }
/* -------------------------------------------------------------------- * AT91RM9200 processor initialization * -------------------------------------------------------------------- */ static void __init at91rm9200_map_io(void) { /* Map peripherals */ at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE); }
static void __init at91sam9263_map_io(void) { at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE); at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE); }
static void __init sama5d3_map_io(void) { at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE); }
/* -------------------------------------------------------------------- * AT91RM9200 processor initialization * -------------------------------------------------------------------- */ static void __init at91rm9200_map_io(void) { /* Map peripherals */ at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE); iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); }
static void __init at91cap9_map_io(void) { at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE); }
static void __init sama5d4_map_io(void) { iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc)); at91_init_sram(0, SAMA5D4_NS_SRAM_BASE, SAMA5D4_NS_SRAM_SIZE); }
static void __init at91sam9g45_map_io(void) { at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE); init_consistent_dma_size(SZ_4M); }