void at91_spl_board_init(void)
{
/*
* For on the sam9m10g45ek board, the chip wm9711 stay in the test
* mode, so it need do some action to exit mode.
*/
at91_set_gpio_output(AT91_PIN_PD7, 0);
at91_set_gpio_output(AT91_PIN_PD8, 0);
at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
corvus_nand_hw_init();
/* Configure recovery button PINs */
at91_set_gpio_input(AT91_PIN_PB7, 1);
/* check if button is pressed */
if (at91_get_gpio_value(AT91_PIN_PB7) == 0) {
u32 boot_device;
debug("Recovery button pressed\n");
boot_device = spl_boot_device();
switch (boot_device) {
#ifdef CONFIG_SPL_NAND_SUPPORT
case BOOT_DEVICE_NAND:
nand_init();
spl_nand_erase_one(0, 0);
break;
#endif
}
}
}
int board_early_init_f(void)
{
struct at91_shdwn *shdwn = (struct at91_shdwn *)ATMEL_BASE_SHDWN;
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/*
* make sure the board can be powered on by
* any transition on WKUP
*/
writel(AT91_SHDW_MR_WKMODE0H2L | AT91_SHDW_MR_WKMODE0L2H,
&shdwn->mr);
/* Enable clocks for all PIOs */
writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
(1 << ATMEL_ID_PIOC),
&pmc->pcer);
/* set SCL0 and SDA0 to open drain */
at91_set_pio_output(I2C0_PORT, SCL0_PIN, 1);
at91_set_pio_multi_drive(I2C0_PORT, SCL0_PIN, 1);
at91_set_pio_pullup(I2C0_PORT, SCL0_PIN, 1);
at91_set_pio_output(I2C0_PORT, SDA0_PIN, 1);
at91_set_pio_multi_drive(I2C0_PORT, SDA0_PIN, 1);
at91_set_pio_pullup(I2C0_PORT, SDA0_PIN, 1);
/* set SCL1 and SDA1 to open drain */
at91_set_pio_output(I2C1_PORT, SCL1_PIN, 1);
at91_set_pio_multi_drive(I2C1_PORT, SCL1_PIN, 1);
at91_set_pio_pullup(I2C1_PORT, SCL1_PIN, 1);
at91_set_pio_output(I2C1_PORT, SDA1_PIN, 1);
at91_set_pio_multi_drive(I2C1_PORT, SDA1_PIN, 1);
at91_set_pio_pullup(I2C1_PORT, SDA1_PIN, 1);
return 0;
}
/*
* mux the pin to the "B" internal peripheral role.
*/
int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
#if defined(CPU_HAS_PIO4)
if (pio4_set_pio_func(at91_port, mask, AT91_PIO_CFGR_FUNC_PERIPH_B, use_pullup))
return -1;
#else
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
#if defined(CPU_HAS_PIO3)
writel(readl(&at91_port->abcdsr1) | mask,
&at91_port->abcdsr1);
writel(readl(&at91_port->abcdsr2) & ~mask,
&at91_port->abcdsr2);
#else
writel(mask, &at91_port->bsr);
#endif
writel(mask, &at91_port->pdr);
#endif
}
return 0;
}
static void corvus_macb_hw_init(void)
{
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_EMAC);
/*
* Disable pull-up on:
* RXDV (PA15) => PHY normal mode (not Test mode)
* ERX0 (PA12) => PHY ADDR0
* ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
*
* PHY has internal pull-down
*/
at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
at91_phy_reset();
/* Re-enable pull-up */
at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
/* And the pins. */
at91_macb_hw_init();
}
static void pm9g45_macb_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/*
* PD2 enables the 50MHz oscillator for Ethernet PHY
* 1 - enable
* 0 - disable
*/
at91_set_pio_output(AT91_PIO_PORTD, 2, 1);
at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */
/* Enable clock */
writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
/*
* Disable pull-up on:
* RXDV (PA15) => PHY normal mode (not Test mode)
* ERX0 (PA12) => PHY ADDR0
* ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
*
* PHY has internal pull-down
*/
at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
/* Re-enable pull-up */
at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
at91_macb_hw_init();
}
/*
* mux the pin to the "GPIO" peripheral role.
*/
int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
mask = 1 << pin;
writel(mask, &pio->port[port].idr);
at91_set_pio_pullup(port, pin, use_pullup);
writel(mask, &pio->port[port].per);
}
return 0;
}
/*
* mux the pin to the "GPIO" peripheral role.
*/
int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
writel(mask, &at91_port->per);
}
return 0;
}
/*
* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
* configure it for an input.
*/
int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if (at91_port && (pin < 32)) {
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
writel(mask, &at91_port->odr);
writel(mask, &at91_port->per);
}
return 0;
}
/*
* mux the pin to the "D" internal peripheral role.
*/
int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if (at91_port && (pin < 32)) {
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
writel(readl(&at91_port->abcdsr1) | mask,
&at91_port->abcdsr1);
writel(readl(&at91_port->abcdsr2) | mask,
&at91_port->abcdsr2);
writel(mask, &at91_port->pdr);
}
return 0;
}
/*
* mux the pin to the "A" internal peripheral role.
*/
int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
mask = 1 << pin;
writel(mask, &pio->port[port].idr);
at91_set_pio_pullup(port, pin, use_pullup);
#if defined(CPU_HAS_PIO3)
writel(readl(&pio->port[port].abcdsr1) & ~mask,
&pio->port[port].abcdsr1);
writel(readl(&pio->port[port].abcdsr2) & ~mask,
&pio->port[port].abcdsr2);
#else
writel(mask, &pio->port[port].asr);
#endif
writel(mask, &pio->port[port].pdr);
}
return 0;
}
/*
* mux the pin to the "A" internal peripheral role.
*/
int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
#if defined(CPU_HAS_PIO3)
writel(readl(&at91_port->abcdsr1) & ~mask,
&at91_port->abcdsr1);
writel(readl(&at91_port->abcdsr2) & ~mask,
&at91_port->abcdsr2);
#else
writel(mask, &at91_port->asr);
#endif
writel(mask, &at91_port->pdr);
}
return 0;
}
