static void __init ath79_usb_setup(void)
{
void __iomem *usb_ctrl_base;
ath79_device_reset_set(AR71XX_USB_RESET_MASK);
mdelay(1000);
ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
/* Turning on the Buff and Desc swap bits */
__raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
/* WAR for HW bug. Here it adjusts the duration between two SOFS */
__raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
iounmap(usb_ctrl_base);
mdelay(900);
ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE,
AR71XX_OHCI_SIZE, ATH79_MISC_IRQ_OHCI);
platform_device_register(&ath79_ohci_device);
ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE,
AR71XX_EHCI_SIZE, ATH79_CPU_IRQ_USB);
ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1;
platform_device_register(&ath79_ehci_device);
}
static void __init ar934x_usb_setup(void)
{
u32 bootstrap;
bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
return;
ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
udelay(1000);
ath79_device_reset_clear(AR934X_RESET_USB_PHY);
udelay(1000);
ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG);
udelay(1000);
ath79_device_reset_clear(AR934X_RESET_USB_HOST);
udelay(1000);
ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE,
AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
platform_device_register(&ath79_ehci_device);
}
static void __init qca955x_usb_setup(void)
{
struct platform_device *pdev;
ath79_usb_init_resource(ath79_ehci_resources,
QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
ATH79_IP3_IRQ(0));
pdev = platform_device_register_resndata(NULL, "ehci-platform", 0,
ath79_ehci_resources,
ARRAY_SIZE(ath79_ehci_resources),
&ath79_ehci_pdata_v2,
sizeof(ath79_ehci_pdata_v2));
if (IS_ERR(pdev)) {
pr_err("Unable to register USB %d device, err=%d\n", 0,
(int) PTR_ERR(pdev));
return;
}
pdev->dev.dma_mask = &ath79_ehci_dmamask;
pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
ath79_usb_init_resource(ath79_ehci_resources,
QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
ATH79_IP3_IRQ(1));
pdev = platform_device_register_resndata(NULL, "ehci-platform", 1,
ath79_ehci_resources,
ARRAY_SIZE(ath79_ehci_resources),
&ath79_ehci_pdata_v2,
sizeof(ath79_ehci_pdata_v2));
if (IS_ERR(pdev)) {
pr_err("Unable to register USB %d device, err=%d\n", 1,
(int) PTR_ERR(pdev));
return;
}
pdev->dev.dma_mask = &ath79_ehci_dmamask;
pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
}
static void __init ar933x_usb_setup(void)
{
ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
mdelay(10);
ath79_device_reset_clear(AR933X_RESET_USB_HOST);
mdelay(10);
ath79_device_reset_clear(AR933X_RESET_USB_PHY);
mdelay(10);
ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE,
AR933X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
platform_device_register(&ath79_ehci_device);
}
static void __init ar7240_usb_setup(void)
{
void __iomem *usb_ctrl_base;
ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
ath79_device_reset_set(AR7240_RESET_USB_HOST);
mdelay(1000);
ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
ath79_device_reset_clear(AR7240_RESET_USB_HOST);
usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
/* WAR for HW bug. Here it adjusts the duration between two SOFS */
__raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
iounmap(usb_ctrl_base);
ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE,
AR7240_OHCI_SIZE, ATH79_CPU_IRQ_USB);
platform_device_register(&ath79_ohci_device);
}
