void sdram_init(void)
{
__maybe_unused struct am335x_baseboard_id header;
puts("sdram_init \n");
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
if (board_is_evm_sk(&header)) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
if (board_is_evm_sk(&header))
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
else if (board_is_bone_lt(&header))
config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
&ddr3_beagleblack_data,
&ddr3_beagleblack_cmd_ctrl_data,
&ddr3_beagleblack_emif_reg_data, 0);
else if (board_is_evm_15_or_later(&header))
config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
else
config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
udelay(500);
}
void config_ddr(short ddr_type)
{
int ddr_pll, ioctrl_val;
const struct emif_regs *emif_regs;
const struct ddr_data *ddr_data;
const struct cmd_control *cmd_ctrl_data;
if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
ddr_pll = 266;
cmd_ctrl_data = &ddr2_cmd_ctrl_data;
ddr_data = &ddr2_data;
ioctrl_val = DDR2_IOCTRL_VALUE;
emif_regs = &ddr2_emif_reg_data;
} else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
ddr_pll = 303;
ioctrl_val = DDR3_IOCTRL_VALUE;
cmd_ctrl_data = &ddr3_cmd_ctrl_data;
if (board_is_evm_15_or_later()) {
ddr_data = &ddr3_evm_data;
emif_regs = &ddr3_evm_emif_reg_data;
} else {
ddr_data = &ddr3_data;
emif_regs = &ddr3_emif_reg_data;
}
} else {
puts("Unknown memory type");
hang();
}
enable_emif_clocks();
ddr_pll_config(ddr_pll);
config_vtp();
config_cmd_ctrl(cmd_ctrl_data);
config_ddr_data(0, ddr_data);
config_ddr_data(1, ddr_data);
config_io_ctrl(ioctrl_val);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
/* Program EMIF instance */
config_ddr_phy(emif_regs);
set_sdram_timings(emif_regs);
config_sdram(emif_regs);
}
const struct dpll_params *get_dpll_ddr_params(void)
{
struct am335x_baseboard_id header;
puts("get_dpll_ddr_params\n");
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
// usleep(2);
if (board_is_evm_sk(&header))
return &dpll_ddr_evm_sk;
else if (board_is_bone_lt(&header))
return &dpll_ddr_bone_black;
else if (board_is_evm_15_or_later(&header))
return &dpll_ddr_evm_sk;
else
return &dpll_ddr;
// usleep(3);
}
/*
* early system init of muxing and clocks.
*/
void s_init(void)
{
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
#ifdef CONFIG_SPL_BUILD
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* Enable RTC32K clock */
rtc32k_enable();
/* UART softreset */
u32 regVal;
#ifdef CONFIG_SERIAL1
enable_uart0_pin_mux();
#endif /* CONFIG_SERIAL1 */
#ifdef CONFIG_SERIAL2
enable_uart1_pin_mux();
#endif /* CONFIG_SERIAL2 */
#ifdef CONFIG_SERIAL3
enable_uart2_pin_mux();
#endif /* CONFIG_SERIAL3 */
#ifdef CONFIG_SERIAL4
enable_uart3_pin_mux();
#endif /* CONFIG_SERIAL4 */
#ifdef CONFIG_SERIAL5
enable_uart4_pin_mux();
#endif /* CONFIG_SERIAL5 */
#ifdef CONFIG_SERIAL6
enable_uart5_pin_mux();
#endif /* CONFIG_SERIAL6 */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_RESET;
writel(regVal, &uart_base->uartsyscfg);
while ((readl(&uart_base->uartsyssts) &
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
;
/* Disable smart idle */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_SMART_IDLE_EN;
writel(regVal, &uart_base->uartsyscfg);
gd = &gdata;
preloader_console_init();
/* Initalize the board header */
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
enable_board_pin_mux(&header);
if (board_is_evm_sk()) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
if (board_is_evm_sk() || board_is_bone_lt())
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
else if (board_is_evm_15_or_later())
config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data);
else
config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
#endif
}
void am33xx_spl_board_init(void)
{
if (!strncmp("A335BONE", header.name, 8)) {
/* BeagleBone PMIC Code */
uchar pmic_status_reg;
if (i2c_probe(TPS65217_CHIP_PM))
return;
if (tps65217_reg_read(STATUS, &pmic_status_reg))
return;
/* Increase USB current limit to 1300mA */
if (tps65217_reg_write(PROT_LEVEL_NONE, POWER_PATH,
USB_INPUT_CUR_LIMIT_1300MA,
USB_INPUT_CUR_LIMIT_MASK))
printf("tps65217_reg_write failure\n");
/* Only perform PMIC configurations if board rev > A1 */
if (!strncmp(header.version, "00A1", 4))
return;
/* Set DCDC2 (MPU) voltage to 1.275V */
if (tps65217_voltage_update(DEFDCDC2,
DCDC_VOLT_SEL_1275MV)) {
printf("tps65217_voltage_update failure\n");
return;
}
/* Set LDO3, LDO4 output voltage to 3.3V */
if (tps65217_reg_write(PROT_LEVEL_2, DEFLS1,
LDO_VOLTAGE_OUT_3_3, LDO_MASK))
printf("tps65217_reg_write failure\n");
if (tps65217_reg_write(PROT_LEVEL_2, DEFLS2,
LDO_VOLTAGE_OUT_3_3, LDO_MASK))
printf("tps65217_reg_write failure\n");
if (!(pmic_status_reg & PWR_SRC_AC_BITMASK)) {
printf("No AC power, disabling frequency switch\n");
return;
}
/* Set MPU Frequency to 720MHz */
mpu_pll_config(MPUPLL_M_720);
} else {
uchar buf[4];
/*
* EVM PMIC code. All boards currently want an MPU voltage
* of 1.2625V and CORE voltage of 1.1375V to operate at
* 720MHz.
*/
if (i2c_probe(PMIC_CTRL_I2C_ADDR))
return;
/* VDD1/2 voltage selection register access by control i/f */
if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
return;
buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
return;
if (!voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) &&
!voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
if (board_is_evm_15_or_later())
mpu_pll_config(MPUPLL_M_800);
else
mpu_pll_config(MPUPLL_M_720);
}
}
}
