/*!
* This function enable and reset GPS GPIO
*/
void gpio_gps_active(void)
{
/* Pull GPIO1_5 to be low for routing signal to UART3/GPS */
if (board_is_mx35(BOARD_REV_2)) {
mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX35_PIN_COMPARE, PAD_CTL_DRV_NORMAL |
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD |
PAD_CTL_SRE_SLOW);
mxc_set_gpio_direction(MX35_PIN_COMPARE, 0);
mxc_set_gpio_dataout(MX35_PIN_COMPARE, 0);
}
/* PWR_EN_GPS is set to be 0, will be toggled on in app by ioctl */
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 0, 0);
/* GPS 32KHz clock enbale */
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 7, 1);
/* GPS reset */
pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 5, 0);
msleep(5);
pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 5, 1);
msleep(5);
}
/*!
* This function disable GPS GPIO
*/
void gpio_gps_inactive(void)
{
/* GPS disable */
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 0, 0);
/* Free GPIO1_5 */
if (board_is_mx35(BOARD_REV_2))
mxc_free_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
}
/*!
* Power Key initialization.
*/
static int __init mxc_init_power_key(void)
{
if (!board_is_mx35(BOARD_REV_2)) {
/*Set power key as wakeup resource */
int irq, ret;
irq = MXC_PSEUDO_IRQ_POWER_KEY;
set_irq_type(irq, IRQF_TRIGGER_RISING);
ret = request_irq(irq, power_key_int, 0, "power_key", 0);
if (ret)
pr_info("register on-off key interrupt failed\n");
else
enable_irq_wake(irq);
return ret;
}
return 0;
}
/*!
* Setup GPIO for spdif tx/rx to be active
*/
void gpio_spdif_active(void)
{
/* SPDIF OUT */
mxc_request_iomux(MX35_PIN_STXD5, MUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX35_PIN_STXD5, PAD_CTL_PKE_NONE | PAD_CTL_PUE_PUD);
/* SPDIF IN */
mxc_request_iomux(MX35_PIN_SRXD5, MUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX35_PIN_SRXD5, PAD_CTL_PKE_ENABLE
| PAD_CTL_100K_PU | PAD_CTL_HYS_SCHMITZ);
/* SPDIF ext clock */
mxc_request_iomux(MX35_PIN_SCK5, MUX_CONFIG_ALT1);
if (board_is_mx35(BOARD_REV_2))
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 5, 1);
else
pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_2, 0, 1);
}
void gpio_fec_inactive(void)
{
mxc_request_gpio(MX35_PIN_FEC_TX_CLK);
mxc_request_gpio(MX35_PIN_FEC_RX_CLK);
mxc_request_gpio(MX35_PIN_FEC_RX_DV);
mxc_request_gpio(MX35_PIN_FEC_COL);
mxc_request_gpio(MX35_PIN_FEC_RDATA0);
mxc_request_gpio(MX35_PIN_FEC_TDATA0);
mxc_request_gpio(MX35_PIN_FEC_TX_EN);
mxc_request_gpio(MX35_PIN_FEC_MDC);
mxc_request_gpio(MX35_PIN_FEC_MDIO);
mxc_request_gpio(MX35_PIN_FEC_TX_ERR);
mxc_request_gpio(MX35_PIN_FEC_RX_ERR);
mxc_request_gpio(MX35_PIN_FEC_CRS);
mxc_request_gpio(MX35_PIN_FEC_RDATA1);
mxc_request_gpio(MX35_PIN_FEC_TDATA1);
mxc_request_gpio(MX35_PIN_FEC_RDATA2);
mxc_request_gpio(MX35_PIN_FEC_TDATA2);
mxc_request_gpio(MX35_PIN_FEC_RDATA3);
mxc_request_gpio(MX35_PIN_FEC_TDATA3);
mxc_free_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_GPIO);
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 2, 0);
/* Free GPIO1_5 */
if (board_is_mx35(BOARD_REV_2))
mxc_free_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
}
/*
* USB Host2
*/
int gpio_usbh2_active(void)
{
if (board_is_mx35(BOARD_REV_2)) {
/* MUX3_CTR to be low for USB Host2 DP&DM */
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 6, 0);
/* CAN_PWDN to be high for USB Host2 Power&OC */
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 1, 1);
}
mxc_request_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX35_PIN_I2C2_CLK, 0x0040);
mxc_request_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_ALT2);
mxc_iomux_set_input(MUX_IN_USB_UH2_USB_OC, INPUT_CTL_PATH0);
mxc_iomux_set_pad(MX35_PIN_I2C2_DAT, 0x01c0);
return 0;
}
/*!
* This function activates DAM ports 5 to enable
* audio I/O.
*/
void gpio_activate_bt_audio_port(void)
{
unsigned int pad_val;
mxc_request_iomux(MX35_PIN_STXD5, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_SRXD5, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_SCK5, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_STXFS5, MUX_CONFIG_FUNC);
pad_val = PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
PAD_CTL_PUE_PUD;
mxc_iomux_set_pad(MX35_PIN_STXD5, pad_val);
mxc_iomux_set_pad(MX35_PIN_SRXD5, pad_val);
mxc_iomux_set_pad(MX35_PIN_SCK5, pad_val);
mxc_iomux_set_pad(MX35_PIN_STXFS5, pad_val);
if (board_is_mx35(BOARD_REV_2))
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 5, 0);
else
pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_2, 0, 0);
}
/*!
* This function is used to set cpu low power mode before WFI instruction
*
* @param mode indicates different kinds of power modes
*/
void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
{
unsigned int lpm;
unsigned long reg;
/*read CCMR value */
reg = __raw_readl(MXC_CCM_CCMR);
switch (mode) {
case WAIT_UNCLOCKED_POWER_OFF:
lpm = MX35_DOZE_MODE;
break;
case STOP_POWER_ON:
case STOP_POWER_OFF:
lpm = MX35_STOP_MODE;
/* Enabled Well Bias */
reg |= MXC_CCM_CCMR_WBEN;
if (board_is_mx35(BOARD_REV_2))
reg |= MXC_CCM_CCMR_VSTBY;
break;
case WAIT_CLOCKED:
case WAIT_UNCLOCKED:
default:
/* Wait is the default mode used when idle. */
lpm = MX35_WAIT_MODE;
break;
}
/* program LPM bit */
reg = (reg & (~MXC_CCM_CCMR_LPM_MASK)) | lpm << MXC_CCM_CCMR_LPM_OFFSET;
/* program Interrupt holdoff bit */
reg = reg | MXC_CCM_CCMR_WFI;
/* TBD: PMIC has put the voltage back to Normal if the voltage ready */
/* counter finished */
reg = reg | MXC_CCM_CCMR_STBY_EXIT_SRC;
__raw_writel(reg, MXC_CCM_CCMR);
}
/*!
* Board specific initialization.
*/
static void __init mxc_board_init(void)
{
mxc_cpu_common_init();
mxc_clocks_init();
early_console_setup(saved_command_line);
mxc_gpio_init();
mxc_init_devices();
if (!board_is_mx35(BOARD_REV_2))
mx35_3stack_fixup_for_board_v1();
mx35_3stack_gpio_init();
mxc_init_enet();
mxc_init_nor_mtd();
mxc_init_nand_mtd();
mxc_init_lcd();
i2c_register_board_info(0, mxc_i2c_board_info,
ARRAY_SIZE(mxc_i2c_board_info));
spi_register_board_info(mxc_spi_board_info,
ARRAY_SIZE(mxc_spi_board_info));
mxc_init_mmc();
}
/*!
* Setup GPIO for SDHC to be active
*
* @param module SDHC module number
*/
void gpio_sdhc_active(int module)
{
unsigned int pad_val;
switch (module) {
case 0:
mxc_request_iomux(MX35_PIN_SD1_CLK,
MUX_CONFIG_FUNC | MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_SD1_CMD,
MUX_CONFIG_FUNC | MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_SD1_DATA0,
MUX_CONFIG_FUNC | MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_SD1_DATA1,
MUX_CONFIG_FUNC | MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_SD1_DATA2,
MUX_CONFIG_FUNC | MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_SD1_DATA3,
MUX_CONFIG_FUNC | MUX_CONFIG_SION);
#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE)
#else
/* MUX4_CTR , 0: SD2 to WIFI, 1:SD2 to SD1 8bit */
if (board_is_mx35(BOARD_REV_2))
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2,
7, 1);
mxc_request_iomux(MX35_PIN_SD2_CMD,
MUX_CONFIG_ALT2 | MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_SD2_CLK,
MUX_CONFIG_ALT2 | MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_SD2_DATA0,
MUX_CONFIG_ALT2 | MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_SD2_DATA1,
MUX_CONFIG_ALT2 | MUX_CONFIG_SION);
#endif
pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
PAD_CTL_47K_PU | PAD_CTL_SRE_FAST;
mxc_iomux_set_pad(MX35_PIN_SD1_CMD, pad_val);
mxc_iomux_set_pad(MX35_PIN_SD1_DATA0, pad_val);
mxc_iomux_set_pad(MX35_PIN_SD1_DATA1, pad_val);
mxc_iomux_set_pad(MX35_PIN_SD1_DATA2, pad_val);
pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
PAD_CTL_DRV_MAX | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST;
mxc_iomux_set_pad(MX35_PIN_SD1_CLK, pad_val);
pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, pad_val);
#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE)
#else
pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
PAD_CTL_47K_PU | PAD_CTL_SRE_FAST;
mxc_iomux_set_pad(MX35_PIN_SD2_CMD, pad_val);
mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, pad_val);
mxc_iomux_set_pad(MX35_PIN_SD2_DATA1, pad_val);
pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
PAD_CTL_DRV_MAX | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST;
mxc_iomux_set_pad(MX35_PIN_SD2_CLK, pad_val);
#endif
break;
case 1:
/* MUX4_CTR , 0: SD2 to WIFI, 1:SD2 to SD1 8bit */
if (board_is_mx35(BOARD_REV_2))
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2,
7, 0);
mxc_request_iomux(MX35_PIN_SD2_CLK,
MUX_CONFIG_FUNC | MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_SD2_CMD,
MUX_CONFIG_FUNC | MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_SD2_DATA0,
MUX_CONFIG_FUNC | MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_SD2_DATA1,
MUX_CONFIG_FUNC | MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_SD2_DATA2,
MUX_CONFIG_FUNC | MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_SD2_DATA3,
MUX_CONFIG_FUNC | MUX_CONFIG_SION);
pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
PAD_CTL_47K_PU | PAD_CTL_SRE_FAST;
mxc_iomux_set_pad(MX35_PIN_SD2_CLK, pad_val);
mxc_iomux_set_pad(MX35_PIN_SD2_CMD, pad_val);
mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, pad_val);
mxc_iomux_set_pad(MX35_PIN_SD2_DATA1, pad_val);
mxc_iomux_set_pad(MX35_PIN_SD2_DATA2, pad_val);
pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, pad_val);
break;
default:
break;
}
}
void gpio_fec_active(void)
{
mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
#define FEC_PAD_CTL_COMMON (PAD_CTL_DRV_3_3V|PAD_CTL_PUE_PUD| \
PAD_CTL_ODE_CMOS|PAD_CTL_DRV_NORMAL|PAD_CTL_SRE_SLOW)
mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, FEC_PAD_CTL_COMMON |
PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_COL,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS |
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS |
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_MDC,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS |
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_MDIO,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU);
mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS |
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_CRS,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS |
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS |
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3,
FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS |
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
#undef FEC_PAD_CTL_COMMON
/* Pull GPIO1_5 to be high for routing signal to FEC */
if (board_is_mx35(BOARD_REV_2)) {
mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX35_PIN_COMPARE, PAD_CTL_DRV_NORMAL |
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD |
PAD_CTL_SRE_SLOW);
mxc_set_gpio_direction(MX35_PIN_COMPARE, 0);
mxc_set_gpio_dataout(MX35_PIN_COMPARE, 1);
}
/* FEC enable */
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 2, 1);
/* FEC reset */
pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 7, 0);
msleep(10);
pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 7, 1);
msleep(100);
}
