static void
brgphy_reset(struct mii_softc *sc)
{
struct bge_softc *bge_sc = NULL;
struct bce_softc *bce_sc = NULL;
struct ifnet *ifp;
int i, val;
/*
* Perform a reset. Note that at least some Broadcom PHYs default to
* being powered down as well as isolated after a reset but don't work
* if one or both of these bits are cleared. However, they just work
* fine if both bits remain set, so we don't use mii_phy_reset() here.
*/
PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
/* Wait 100ms for it to complete. */
for (i = 0; i < 100; i++) {
if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0)
break;
DELAY(1000);
}
/* Handle any PHY specific procedures following the reset. */
switch (sc->mii_mpd_oui) {
case MII_OUI_BROADCOM:
switch (sc->mii_mpd_model) {
case MII_MODEL_BROADCOM_BCM5400:
bcm5401_load_dspcode(sc);
break;
case MII_MODEL_BROADCOM_BCM5401:
if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
bcm5401_load_dspcode(sc);
break;
case MII_MODEL_BROADCOM_BCM5411:
bcm5411_load_dspcode(sc);
break;
case MII_MODEL_BROADCOM_BCM54K2:
bcm54k2_load_dspcode(sc);
break;
}
break;
case MII_OUI_BROADCOM3:
switch (sc->mii_mpd_model) {
case MII_MODEL_BROADCOM3_BCM5717C:
case MII_MODEL_BROADCOM3_BCM5719C:
case MII_MODEL_BROADCOM3_BCM5720C:
case MII_MODEL_BROADCOM3_BCM57765:
return;
}
break;
case MII_OUI_BROADCOM4:
return;
}
ifp = sc->mii_pdata->mii_ifp;
/* Find the driver associated with this PHY. */
if (strcmp(ifp->if_dname, "bge") == 0) {
bge_sc = ifp->if_softc;
} else if (strcmp(ifp->if_dname, "bce") == 0) {
bce_sc = ifp->if_softc;
}
if (bge_sc) {
/* Fix up various bugs */
if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
brgphy_fixup_5704_a0_bug(sc);
if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
brgphy_fixup_adc_bug(sc);
if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
brgphy_fixup_adjust_trim(sc);
if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
brgphy_fixup_ber_bug(sc);
if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
brgphy_fixup_crc_bug(sc);
if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
brgphy_fixup_jitter_bug(sc);
if (bge_sc->bge_flags & BGE_FLAG_JUMBO)
brgphy_jumbo_settings(sc, ifp->if_mtu);
if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0)
brgphy_ethernet_wirespeed(sc);
/* Enable Link LED on Dell boxes */
if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
~BRGPHY_PHY_EXTCTL_3_LED);
}
/* Adjust output voltage (From Linux driver) */
if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
} else if (bce_sc) {
if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
/* Store autoneg capabilities/results in digital block (Page 0) */
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
/* Enable fiber mode and autodetection */
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
/* Enable parallel detection */
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
/* Advertise 2.5G support through next page during autoneg */
if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
/* Increase TX signal amplitude */
if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
(BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
(BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_TX_MISC_PG5);
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_DIG_PG0);
}
/* Backplanes use special driver/pre-driver/pre-emphasis values. */
if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
(bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_TX_MISC_PG5);
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
bce_sc->bce_port_hw_cfg &
BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_DIG_PG0);
}
} else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
/* Select the SerDes Digital block of the AN MMD. */
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
/* Select the Over 1G block of the AN MMD. */
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
/* Enable autoneg "Next Page" to advertise 2.5G support. */
val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
else
val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
/* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
/* Enable MRBE speed autoneg. */
val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
BRGPHY_MRBE_MSG_PG5_NP_T2;
PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
/* Select the Clause 73 User B0 block of the AN MMD. */
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
/* Enable MRBE speed autoneg. */
PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
/* Restore IEEE0 block (assumed in all brgphy(4) code). */
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
} else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
(BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
brgphy_fixup_disable_early_dac(sc);
brgphy_jumbo_settings(sc, ifp->if_mtu);
brgphy_ethernet_wirespeed(sc);
} else {
brgphy_fixup_ber_bug(sc);
brgphy_jumbo_settings(sc, ifp->if_mtu);
brgphy_ethernet_wirespeed(sc);
}
}
}
static void
brgphy_reset(struct mii_softc *sc)
{
struct brgphy_softc *bsc = device_private(sc->mii_dev);
mii_phy_reset(sc);
switch (sc->mii_mpd_oui) {
case MII_OUI_BROADCOM:
switch (sc->mii_mpd_model) {
case MII_MODEL_BROADCOM_BCM5400:
brgphy_bcm5401_dspcode(sc);
break;
case MII_MODEL_BROADCOM_BCM5401:
if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
brgphy_bcm5401_dspcode(sc);
break;
case MII_MODEL_BROADCOM_BCM5411:
brgphy_bcm5411_dspcode(sc);
break;
case MII_MODEL_BROADCOM_BCM5421:
brgphy_bcm5421_dspcode(sc);
break;
case MII_MODEL_BROADCOM_BCM54K2:
brgphy_bcm54k2_dspcode(sc);
break;
}
break;
case MII_OUI_BROADCOM3:
switch (sc->mii_mpd_model) {
case MII_MODEL_BROADCOM3_BCM5717C:
case MII_MODEL_BROADCOM3_BCM5719C:
case MII_MODEL_BROADCOM3_BCM5720C:
case MII_MODEL_BROADCOM3_BCM57765:
return;
}
break;
default:
break;
}
/* Handle any bge (NetXtreme/NetLink) workarounds. */
if (bsc->sc_isbge) {
if (!(sc->mii_flags & MIIF_HAVEFIBER)) {
if (bsc->sc_phyflags & BGEPHYF_ADC_BUG)
brgphy_adc_bug(sc);
if (bsc->sc_phyflags & BGEPHYF_5704_A0_BUG)
brgphy_5704_a0_bug(sc);
if (bsc->sc_phyflags & BGEPHYF_BER_BUG)
brgphy_ber_bug(sc);
else if (bsc->sc_phyflags & BGEPHYF_JITTER_BUG) {
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG,
0x000a);
if (bsc->sc_phyflags
& BGEPHYF_ADJUST_TRIM) {
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT,
0x110b);
PHY_WRITE(sc, BRGPHY_TEST1,
BRGPHY_TEST1_TRIM_EN | 0x4);
} else {
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT,
0x010b);
}
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
}
if (bsc->sc_phyflags & BGEPHYF_CRC_BUG)
brgphy_crc_bug(sc);
/* Set Jumbo frame settings in the PHY. */
if (bsc->sc_phyflags & BGEPHYF_JUMBO_CAPABLE)
brgphy_jumbo_settings(sc);
/* Adjust output voltage */
if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
&& (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906))
PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
/* Enable Ethernet@Wirespeed */
if (!(bsc->sc_phyflags & BGEPHYF_NO_WIRESPEED))
brgphy_eth_wirespeed(sc);
#if 0
/* Enable Link LED on Dell boxes */
if (bsc->sc_phyflags & BGEPHYF_NO_3LED) {
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
& ~BRGPHY_PHY_EXTCTL_3_LED);
}
#endif
}
/* Handle any bnx (NetXtreme II) workarounds. */
} else if (bsc->sc_isbnx) {
#if 0 /* not yet */
if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
&& sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) {
/* Store autoneg capabilities/results in digital block (Page 0) */
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
/* Enable fiber mode and autodetection */
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
/* Enable parallel detection */
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
/* Advertise 2.5G support through next page during autoneg */
if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG)
PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
/* Increase TX signal amplitude */
if ((BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_A0) ||
(BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B0) ||
(BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B1)) {
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_TX_MISC_PG5);
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) &
~BRGPHY_5708S_PG5_TXACTL1_VCM);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_DIG_PG0);
}
/* Backplanes use special driver/pre-driver/pre-emphasis values. */
if ((bnx_sc->bnx_shared_hw_cfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) &&
(bnx_sc->bnx_port_hw_cfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_TX_MISC_PG5);
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
bnx_sc->bnx_port_hw_cfg &
BNX_PORT_HW_CFG_CFG_TXCTL3_MASK);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_DIG_PG0);
}
} else
#endif
if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
&& (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) {
/* Select the SerDes Digital block of the AN MMD. */
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
BRGPHY_BLOCK_ADDR_SERDES_DIG);
PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1,
(PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1) &
~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) |
BRGPHY_SD_DIG_1000X_CTL1_FIBER);
if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) {
/* Select the Over 1G block of the AN MMD. */
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
BRGPHY_BLOCK_ADDR_OVER_1G);
/*
* Enable autoneg "Next Page" to advertise
* 2.5G support.
*/
PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1,
PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1) |
BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
}
/*
* Select the Multi-Rate Backplane Ethernet block of
* the AN MMD.
*/
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
BRGPHY_BLOCK_ADDR_MRBE);
/* Enable MRBE speed autoneg. */
PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP,
PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP) |
BRGPHY_MRBE_MSG_PG5_NP_MBRE |
BRGPHY_MRBE_MSG_PG5_NP_T2);
/* Select the Clause 73 User B0 block of the AN MMD. */
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
BRGPHY_BLOCK_ADDR_CL73_USER_B0);
/* Enable MRBE speed autoneg. */
PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
} else if (_BNX_CHIP_NUM(bsc->sc_chipid) == BNX_CHIP_NUM_5709) {
if (_BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Ax ||
_BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Bx)
brgphy_disable_early_dac(sc);
/* Set Jumbo frame settings in the PHY. */
brgphy_jumbo_settings(sc);
/* Enable Ethernet@Wirespeed */
brgphy_eth_wirespeed(sc);
} else {
if (!(sc->mii_flags & MIIF_HAVEFIBER)) {
brgphy_ber_bug(sc);
/* Set Jumbo frame settings in the PHY. */
brgphy_jumbo_settings(sc);
/* Enable Ethernet@Wirespeed */
brgphy_eth_wirespeed(sc);
}
}
}
}
static void
brgphy_reset(struct mii_softc *sc)
{
mii_phy_reset(sc);
switch (sc->mii_model) {
case MII_MODEL_xxBROADCOM_BCM5400:
brgphy_bcm5401_dspcode(sc);
break;
case MII_MODEL_xxBROADCOM_BCM5401:
if (sc->mii_rev == 1 || sc->mii_rev == 3)
brgphy_bcm5401_dspcode(sc);
break;
case MII_MODEL_xxBROADCOM_BCM5411:
brgphy_bcm5411_dspcode(sc);
break;
case MII_MODEL_xxBROADCOM_BCM5421:
brgphy_bcm5421_dspcode(sc);
break;
case MII_MODEL_xxBROADCOM_BCM54K2:
brgphy_bcm54k2_dspcode(sc);
break;
}
if (sc->mii_privtag != MII_PRIVTAG_BRGPHY)
return;
if (sc->mii_priv & BRGPHY_FLAG_ADC_BUG)
brgphy_adc_bug(sc);
if (sc->mii_priv & BRGPHY_FLAG_5704_A0)
brgphy_5704_a0_bug(sc);
if (sc->mii_priv & BRGPHY_FLAG_BER_BUG) {
brgphy_ber_bug(sc);
} else if (sc->mii_priv & BRGPHY_FLAG_JITTER_BUG) {
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
if (sc->mii_priv & BRGPHY_FLAG_ADJUST_TRIM) {
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x110b);
PHY_WRITE(sc, BRGPHY_TEST1,
BRGPHY_TEST1_TRIM_EN | 0x4);
} else {
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x010b);
}
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
}
if (sc->mii_priv & BRGPHY_FLAG_CRC_BUG)
brgphy_crc_bug(sc);
if (sc->mii_priv & BRGPHY_FLAG_NO_EARLYDAC)
brgphy_disable_early_dac(sc);
/* Set Jumbo frame settings in the PHY. */
brgphy_jumbo_settings(sc, sc->mii_pdata->mii_ifp->if_mtu);
/* Adjust output voltage */
if (sc->mii_priv & BRGPHY_FLAG_5906)
PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
/* Enable Ethernet@Wirespeed */
if (sc->mii_priv & BRGPHY_FLAG_WIRESPEED)
brgphy_eth_wirespeed(sc);
/* Enable Link LED on Dell boxes */
if (sc->mii_priv & BRGPHY_FLAG_NO_3LED) {
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
~BRGPHY_PHY_EXTCTL_3_LED);
}
}
static void
brgphy_reset(struct mii_softc *sc)
{
struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
struct bge_softc *bge_sc = NULL;
struct bce_softc *bce_sc = NULL;
struct ifnet *ifp;
/* Perform a standard PHY reset. */
mii_phy_reset(sc);
/* Handle any PHY specific procedures following the reset. */
switch (bsc->mii_oui) {
case MII_OUI_BROADCOM:
break;
case MII_OUI_xxBROADCOM:
switch (bsc->mii_model) {
case MII_MODEL_xxBROADCOM_BCM5400:
bcm5401_load_dspcode(sc);
break;
case MII_MODEL_xxBROADCOM_BCM5401:
if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
bcm5401_load_dspcode(sc);
break;
case MII_MODEL_xxBROADCOM_BCM5411:
bcm5411_load_dspcode(sc);
break;
}
break;
case MII_OUI_xxBROADCOM_ALT1:
break;
}
ifp = sc->mii_pdata->mii_ifp;
/* Find the driver associated with this PHY. */
if (strcmp(ifp->if_dname, "bge") == 0) {
bge_sc = ifp->if_softc;
} else if (strcmp(ifp->if_dname, "bce") == 0) {
bce_sc = ifp->if_softc;
}
/* Handle any bge (NetXtreme/NetLink) workarounds. */
if (bge_sc) {
/* Fix up various bugs */
if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
brgphy_fixup_5704_a0_bug(sc);
if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG)
brgphy_fixup_adc_bug(sc);
if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM)
brgphy_fixup_adjust_trim(sc);
if (bge_sc->bge_flags & BGE_FLAG_BER_BUG)
brgphy_fixup_ber_bug(sc);
if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG)
brgphy_fixup_crc_bug(sc);
if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG)
brgphy_fixup_jitter_bug(sc);
brgphy_jumbo_settings(sc, ifp->if_mtu);
if (bge_sc->bge_flags & BGE_FLAG_WIRESPEED)
brgphy_ethernet_wirespeed(sc);
/* Enable Link LED on Dell boxes */
if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) {
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
~BRGPHY_PHY_EXTCTL_3_LED);
}
/* Adjust output voltage (From Linux driver) */
if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
/* Handle any bce (NetXtreme II) workarounds. */
} else if (bce_sc) {
if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
/* Store autoneg capabilities/results in digital block (Page 0) */
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
/* Enable fiber mode and autodetection */
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
/* Enable parallel detection */
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
/* Advertise 2.5G support through next page during autoneg */
if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
/* Increase TX signal amplitude */
if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
(BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
(BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_TX_MISC_PG5);
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_DIG_PG0);
}
/* Backplanes use special driver/pre-driver/pre-emphasis values. */
if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
(bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_TX_MISC_PG5);
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
bce_sc->bce_port_hw_cfg &
BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_DIG_PG0);
}
} else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
(BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
brgphy_fixup_disable_early_dac(sc);
brgphy_jumbo_settings(sc, ifp->if_mtu);
brgphy_ethernet_wirespeed(sc);
} else {
brgphy_fixup_ber_bug(sc);
brgphy_jumbo_settings(sc, ifp->if_mtu);
brgphy_ethernet_wirespeed(sc);
}
}
}
void
brgphy_reset_bnx(struct mii_softc *sc)
{
struct bnx_softc *bnx_sc = sc->mii_pdata->mii_ifp->if_softc;
if (BNX_CHIP_NUM(bnx_sc) == BNX_CHIP_NUM_5708 &&
sc->mii_flags & MIIF_HAVEFIBER) {
/* Store autoneg capabilities/results in digital block (Page 0) */
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
/* Enable fiber mode and autodetection */
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
/* Enable parallel detection */
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
/* Advertise 2.5G support through next page during autoneg */
if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) {
PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
}
/* Increase TX signal amplitude */
if ((BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_A0) ||
(BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B0) ||
(BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B1)) {
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_TX_MISC_PG5);
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) &
~BRGPHY_5708S_PG5_TXACTL1_VCM);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_DIG_PG0);
}
/* Backplanes use special driver/pre-driver/pre-emphasis values. */
if ((bnx_sc->bnx_shared_hw_cfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) &&
(bnx_sc->bnx_port_hw_cfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_TX_MISC_PG5);
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
bnx_sc->bnx_port_hw_cfg &
BNX_PORT_HW_CFG_CFG_TXCTL3_MASK);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_DIG_PG0);
}
} else if (BNX_CHIP_NUM(bnx_sc) == BNX_CHIP_NUM_5709 &&
sc->mii_flags & MIIF_HAVEFIBER) {
/* Select the SerDes Digital block of the AN MMD. */
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1,
(PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1) &
~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) |
BRGPHY_SD_DIG_1000X_CTL1_FIBER);
if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) {
/* Select the Over 1G block of the AN MMD. */
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
BRGPHY_BLOCK_ADDR_OVER_1G);
/*
* Enable autoneg "Next Page" to advertise
* 2.5G support.
*/
PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1,
PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1) |
BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
}
/*
* Select the Multi-Rate Backplane Ethernet block of
* the AN MMD.
*/
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
/* Enable MRBE speed autoneg. */
PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP,
PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP) |
BRGPHY_MRBE_MSG_PG5_NP_MBRE |
BRGPHY_MRBE_MSG_PG5_NP_T2);
/* Select the Clause 73 User B0 block of the AN MMD. */
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
BRGPHY_BLOCK_ADDR_CL73_USER_B0);
/* Enable MRBE speed autoneg. */
PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
} else if (BNX_CHIP_NUM(bnx_sc) == BNX_CHIP_NUM_5709) {
if (BNX_CHIP_REV(bnx_sc) == BNX_CHIP_REV_Ax ||
BNX_CHIP_REV(bnx_sc) == BNX_CHIP_REV_Bx)
brgphy_disable_early_dac(sc);
/* Set Jumbo frame settings in the PHY. */
brgphy_jumbo_settings(sc);
/* Enable Ethernet@Wirespeed */
brgphy_eth_wirespeed(sc);
} else if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
brgphy_ber_bug(sc);
/* Set Jumbo frame settings in the PHY. */
brgphy_jumbo_settings(sc);
/* Enable Ethernet@Wirespeed */
brgphy_eth_wirespeed(sc);
}
}
void
brgphy_reset_bge(struct mii_softc *sc)
{
struct bge_softc *bge_sc = sc->mii_pdata->mii_ifp->if_softc;
if (sc->mii_flags & MIIF_HAVEFIBER)
return;
switch (sc->mii_oui) {
case MII_OUI_xxBROADCOM3:
switch (sc->mii_model) {
case MII_MODEL_xxBROADCOM3_BCM5717C:
case MII_MODEL_xxBROADCOM3_BCM5719C:
case MII_MODEL_xxBROADCOM3_BCM5720C:
case MII_MODEL_xxBROADCOM3_BCM57765:
return;
}
}
if (bge_sc->bge_flags & BGE_PHY_ADC_BUG)
brgphy_adc_bug(sc);
if (bge_sc->bge_flags & BGE_PHY_5704_A0_BUG)
brgphy_5704_a0_bug(sc);
if (bge_sc->bge_flags & BGE_PHY_BER_BUG)
brgphy_ber_bug(sc);
else if (bge_sc->bge_flags & BGE_PHY_JITTER_BUG) {
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
if (bge_sc->bge_flags & BGE_PHY_ADJUST_TRIM) {
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x110b);
PHY_WRITE(sc, BRGPHY_TEST1, BRGPHY_TEST1_TRIM_EN |
0x4);
} else
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x010b);
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
}
if (bge_sc->bge_flags & BGE_PHY_CRC_BUG)
brgphy_crc_bug(sc);
/* Set Jumbo frame settings in the PHY. */
if (bge_sc->bge_flags & BGE_JUMBO_CAPABLE)
brgphy_jumbo_settings(sc);
/* Adjust output voltage */
if (sc->mii_oui == MII_OUI_BROADCOM2 &&
sc->mii_model == MII_MODEL_BROADCOM2_BCM5906)
PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
/* Enable Ethernet@Wirespeed */
if (!(bge_sc->bge_flags & BGE_NO_ETH_WIRE_SPEED))
brgphy_eth_wirespeed(sc);
/* Enable Link LED on Dell boxes */
if (bge_sc->bge_flags & BGE_NO_3LED) {
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
& ~BRGPHY_PHY_EXTCTL_3_LED);
}
}