/*
* Attach the peripheral bus.
*/
static void
pbus_attach(struct device *parent, struct device *self, void *aux)
{
struct plb_attach_args *paa = aux;
struct pbus_attach_args pba;
int i;
#if NPCKBC > 0
bus_space_handle_t ioh_fpga;
bus_space_tag_t iot_fpga = &pbus_tag;
uint8_t fpga_reg;
#endif
printf("\n");
if (bus_space_init(&pbus_tag, "pbus", NULL, 0))
panic("pbus_attach: can't init tag");
for (i = 0; pbus_devs[i].name != NULL; i++) {
pba.pb_name = pbus_devs[i].name;
pba.pb_addr = pbus_devs[i].addr;
pba.pb_irq = pbus_devs[i].irq;
pba.pb_bt = &pbus_tag;
pba.pb_dmat = paa->plb_dmat;
(void) config_found_sm(self, &pba, pbus_print, pbus_submatch);
}
#if NPCKBC > 0
/* Configure FPGA */
if (bus_space_map(iot_fpga, FPGA_BASE, FPGA_SIZE, 0, &ioh_fpga)) {
printf("pbus_attach: can't map FPGA\n");
/* XXX - disable keyboard probe? */
} else {
/* Use separate interrupts for keyboard and mouse */
fpga_reg = bus_space_read_1(iot_fpga, ioh_fpga, FPGA_BRDC);
fpga_reg |= FPGA_BRDC_INT;
bus_space_write_1(iot_fpga, ioh_fpga, FPGA_BRDC, fpga_reg);
/* Set interrupts to active high */
fpga_reg = bus_space_read_1(iot_fpga, ioh_fpga, FPGA_INT_POL);
fpga_reg |= (FPGA_IRQ_KYBD | FPGA_IRQ_MOUSE);
bus_space_write_1(iot_fpga, ioh_fpga, FPGA_INT_POL, fpga_reg);
/* Set interrupts to level triggered */
fpga_reg = bus_space_read_1(iot_fpga, ioh_fpga, FPGA_INT_TRIG);
fpga_reg |= (FPGA_IRQ_KYBD | FPGA_IRQ_MOUSE);
bus_space_write_1(iot_fpga, ioh_fpga, FPGA_INT_TRIG, fpga_reg);
/* Enable interrupts */
fpga_reg = bus_space_read_1(iot_fpga, ioh_fpga, FPGA_INT_ENABLE);
fpga_reg |= (FPGA_IRQ_KYBD | FPGA_IRQ_MOUSE);
bus_space_write_1(iot_fpga, ioh_fpga, FPGA_INT_ENABLE, fpga_reg);
bus_space_unmap(&iot_fpga, ioh_fpga, 2);
}
#endif
}
void
pci_machdep_init(void)
{
if (pci_ioh == 0 &&
(bus_space_init(&pci_iot, "pcicfg", NULL, 0) ||
bus_space_map(&pci_iot, IBM405GP_PCIC0_BASE, 8, 0, &pci_ioh)))
panic("Cannot map PCI registers");
}
static void
setup_pcicfg_window(void)
{
if (pcicfg_ioh)
return;
if (bus_space_init(&pcicfg_tag,
"pcicfg", ex_storage, sizeof(ex_storage)) ||
bus_space_map(pcicfg_iot, 0, 0x40 , 0, &pcicfg_ioh))
panic("Cannot map PCI configuration registers");
}
bus_space_tag_t
opb_get_bus_space_tag(void)
{
int i, pvr;
if (!opb_tag_init_done) {
pvr = mfpvr() >> 16;
for (i = 0; opb_limits[i].pvr && opb_limits[i].pvr != pvr; i++)
;
if (opb_limits[i].pvr == 0)
panic("opb_get_bus_space_tag: no limits for this CPU!");
opb_tag.pbs_base = opb_limits[i].base;
opb_tag.pbs_limit = opb_limits[i].limit;
if (bus_space_init(&opb_tag, "opbtag",
ex_storage, sizeof(ex_storage)))
panic("opb_attach: Failed to initialise opb_tag");
opb_tag_init_done = 1;
}
static void
dwctwo_plb_attach(device_t parent, device_t self, void *aux)
{
struct dwc2_softc *sc = device_private(self);
struct plb_attach_args *paa = aux;
prop_dictionary_t dict = device_properties(self);
uint32_t srst0;
sc->sc_dev = self;
/* get core parameters */
if (!prop_dictionary_get_uint32(dict, "params",
(uint32_t *)&sc->sc_params)) {
aprint_error("struct dwc2_core_params not found\n");
return;
}
dwctwo_tag.pbs_base = paa->plb_addr;
dwctwo_tag.pbs_limit += paa->plb_addr;
if (bus_space_init(&dwctwo_tag, "dwctwotag", ex_storage,
sizeof(ex_storage)))
panic("dwctwo_attach: Failed to initialise opb_tag");
sc->sc_iot = &dwctwo_tag;
bus_space_map(sc->sc_iot, paa->plb_addr, DWCTWO_SIZE, 0, &sc->sc_ioh);
sc->sc_bus.dmatag = paa->plb_dmat;
intr_establish(paa->plb_irq, IST_LEVEL, IPL_SCHED, dwc2_intr, sc);
/* Enable the USB interface. */
mtsdr(DCR_SDR0_PFC1, mfsdr(DCR_SDR0_PFC1) | SDR0_PFC1_USBEN);
srst0 = mfsdr(DCR_SDR0_SRST0);
mtsdr(DCR_SDR0_SRST0, srst0 | SDR0_SRST0_UPRST | SDR0_SRST0_AHB);
delay(200 * 1000); /* XXXX */
mtsdr(DCR_SDR0_SRST0, srst0);
config_defer(self, dwctwo_plb_deferred);
}
static void
pchbattach(device_t parent, device_t self, void *aux)
{
struct plb_attach_args *paa = aux;
struct pcibus_attach_args pba;
char devinfo[256];
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#ifdef PCI_CONFIGURE_VERBOSE
extern int pci_conf_debug;
pci_conf_debug = 1;
#endif
#endif
pci_chipset_tag_t pc = 0;
pcitag_t tag;
int class, id;
pci_machdep_init();
tag = pci_make_tag(pc, 0, 0, 0);
class = pci_conf_read(pc, tag, PCI_CLASS_REG);
id = pci_conf_read(pc, tag, PCI_ID_REG);
aprint_normal("\n");
pcifound = true;
/*
* All we do is print out a description. Eventually, we
* might want to add code that does something that's
* possibly chipset-specific.
*/
pci_devinfo(id, class, 0, devinfo, sizeof(devinfo));
aprprint_normal_dev(self, "%s (rev. 0x%02x)\n", devinfo,
PCI_REVISION(class));
pci_machdep_init(); /* Redundant... */
ibm4xx_setup_pci();
#ifdef PCI_CONFIGURE_VERBOSE
ibm4xx_show_pci_map();
#endif
if (bus_space_init(&pchb_io_tag, "pchbio", NULL, 0))
panic("pchbattach: can't init IO tag");
if (bus_space_init(&pchb_mem_tag, "pchbmem", NULL, 0))
panic("pchbattach: can't init MEM tag");
#ifdef PCI_NETBSD_CONFIGURE
memext = extent_create("pcimem", MIN_PCI_MEMADDR_NOPREFETCH,
MIN_PCI_MEMADDR_NOPREFETCH + 0x1fffffff, M_DEVBUF, NULL, 0,
EX_NOWAIT);
ioext = extent_create("pciio", MIN_PCI_PCI_IOADDR,
MIN_PCI_PCI_IOADDR + 0xffff, M_DEVBUF, NULL, 0, EX_NOWAIT);
pci_configure_bus(0, ioext, memext, NULL, 0, 32);
extent_destroy(memext);
extent_destroy(ioext);
#endif /* PCI_NETBSD_CONFIGURE */
#ifdef PCI_CONFIGURE_VERBOSE
printf("running config_found PCI\n");
#endif
/* IO window located @ e8000000 and maps to 0-0xffff */
pba.pba_iot = &pchb_io_tag;
/* PCI memory window is directly mapped */
pba.pba_memt = &pchb_mem_tag;
pba.pba_dmat = paa->plb_dmat;
pba.pba_dmat64 = NULL;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY;
config_found_ia(self, "pcibus", &pba, pchbprint);
}
