static void
sec_attach(device_t parent, device_t self, void *aux)
{
struct podulebus_attach_args *pa = aux;
struct sec_softc *sc = device_private(self);
int i;
sc->sc_sbic.sc_dev = self;
/* Set up bus spaces */
sc->sc_pod_t = pa->pa_fast_t;
bus_space_map(pa->pa_fast_t, pa->pa_fast_base, 0x1000, 0,
&sc->sc_pod_h);
sc->sc_mod_t = pa->pa_mod_t;
bus_space_map(pa->pa_mod_t, pa->pa_mod_base, 0x1000, 0,
&sc->sc_mod_h);
sc->sc_sbic.sc_regt = sc->sc_mod_t;
bus_space_subregion(sc->sc_mod_t, sc->sc_mod_h, SEC_SBIC + 0, 1,
&sc->sc_sbic.sc_asr_regh);
bus_space_subregion(sc->sc_mod_t, sc->sc_mod_h, SEC_SBIC + 1, 1,
&sc->sc_sbic.sc_data_regh);
sc->sc_sbic.sc_id = 7;
sc->sc_sbic.sc_clkfreq = SEC_CLKFREQ;
sc->sc_sbic.sc_dmamode = SBIC_CTL_BURST_DMA;
sc->sc_sbic.sc_adapter.adapt_request = wd33c93_scsi_request;
sc->sc_sbic.sc_adapter.adapt_minphys = minphys;
sc->sc_sbic.sc_dmasetup = sec_dmasetup;
sc->sc_sbic.sc_dmago = sec_dmago;
sc->sc_sbic.sc_dmastop = sec_dmastop;
sc->sc_sbic.sc_reset = sec_reset;
sc->sc_mpr = 0;
bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr);
for (i = 0; i < SEC_NPAGES; i++) {
sec_setpage(sc, i);
bus_space_set_region_2(sc->sc_mod_t, sc->sc_mod_h,
SEC_SRAM, 0, SEC_PAGESIZE / 2);
}
wd33c93_attach(&sc->sc_sbic);
evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
device_xname(self), "intr");
sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO, sec_intr,
sc, &sc->sc_intrcnt);
sec_cli(sc);
sc->sc_mpr |= SEC_MPR_IE;
bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr);
pmf_device_register1(sc->sc_sbic.sc_dev, NULL, NULL, sec_shutdown);
}
void
isa_fillw(u_int val, void *addr, size_t len)
{
if ((u_int)addr >= isa_mem_data_vaddr()
&& (u_int)addr < isa_mem_data_vaddr() + 0x100000) {
bus_size_t offset = ((u_int)addr) & 0xfffff;
bus_space_set_region_2(&isa_mem_bs_tag,
(bus_space_handle_t)isa_mem_bs_tag.bs_cookie, offset,
val, len);
} else {
u_short *ptr = addr;
while (len > 0) {
*ptr++ = val;
--len;
}
}
}
/*
* Zero memory and verify that it is clear. The only difference between
* this and the default test_mem function is that the DP8390-based NuBus
* cards * apparently require word-wide writes and byte-wide reads, an
* `interesting' combination.
*/
int
ae_test_mem(struct dp8390_softc *sc)
{
bus_space_tag_t buft = sc->sc_buft;
bus_space_handle_t bufh = sc->sc_bufh;
int i;
bus_space_set_region_2(buft, bufh, sc->mem_start, 0,
sc->mem_size / 2);
for (i = 0; i < sc->mem_size; ++i) {
if (bus_space_read_1(sc->sc_buft, sc->sc_bufh, i)) {
printf(": failed to clear NIC buffer at offset %x - "
"check configuration\n", (sc->mem_start + i));
return 1;
}
}
return 0;
}
void
bs_through_bs_sr_2(bus_space_tag_t t, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t value, bus_size_t count)
{
bus_space_set_region_2(t->bs_base, bsh, offset, value, count);
}
