u32 cal_get_ids_hpm_group(void) { u32 i; u32 group = 0; if (big_ids >= ids_table_v0[MAX_ASV_GROUP-1]) group = MAX_ASV_GROUP - 1; else if (big_ids <= ids_table_v0[0]) group = 0; else { for (i = MAX_ASV_GROUP; i > 0; i--) { if (big_ids > ids_table_v0[i-1]) { group = i; break; } } } if (cal_get_table_ver() == 0) group = 0; /* Temporary Code for Margin Issue */ else if (cal_get_table_ver() == 1) { if((__raw_readl(CHIPID_ASV_TBL_BASE)&0x1)==1) { if(group < 4) /*Group < 4 -> Group 1 */ group = 1; else group -= 3; /* Group shift -3 for margin */ } } return group; }
int gpu_dvfs_decide_max_clock(struct exynos_context *platform) { int table_id; int level; if (!platform) return -1; table_id = cal_get_table_ver(); if (table_id < 0) return -1; if (table_id >= GPU_DVFS_TABLE_LIST_SIZE(available_max_clock)) table_id = GPU_DVFS_TABLE_LIST_SIZE(available_max_clock)-1; level = available_max_clock[table_id]; platform->gpu_max_clock = MIN(platform->gpu_max_clock, platform->table[level].clock); if (is_max_limit_sample()) platform->gpu_max_clock = MIN(platform->gpu_max_clock, platform->table[GPU_L3].clock); return 0; }
u32 cal_get_freq(u32 id, s32 level) { u32 freq = 0; u32 idx; u32 minlvl = cal_get_min_lv(id); if (level >= minlvl) idx = 0; idx = level; if (cal_get_table_ver() == 0) { freq = ((id == SYSC_DVFS_BIG) ? volt_table_big_v0[idx][0] : (id == SYSC_DVFS_LIT) ? volt_table_lit_v0[idx][0] : (id == SYSC_DVFS_G3D) ? volt_table_g3d_v0[idx][0] : (id == SYSC_DVFS_MIF) ? volt_table_mif_v0[idx][0] : (id == SYSC_DVFS_INT) ? volt_table_int_v0[idx][0] : (id == SYSC_DVFS_CAM) ? volt_table_cam_v0[idx][0] : 0); } else if (cal_get_table_ver() <= 4) { /* table ver 1, 2, 3, 4 */ freq = ((id == SYSC_DVFS_BIG) ? volt_table_big_v1[idx][0] : (id == SYSC_DVFS_LIT) ? volt_table_lit_v1[idx][0] : (id == SYSC_DVFS_G3D) ? volt_table_g3d_v1[idx][0] : (id == SYSC_DVFS_MIF) ? volt_table_mif_v1[idx][0] : (id == SYSC_DVFS_INT) ? volt_table_int_v1[idx][0] : (id == SYSC_DVFS_CAM) ? volt_table_cam_v1[idx][0] : 0); } else if (cal_get_table_ver() == 5) { /* table ver 5 */ freq = ((id == SYSC_DVFS_BIG) ? volt_table_big_v2[idx][0] : (id == SYSC_DVFS_LIT) ? volt_table_lit_v2[idx][0] : (id == SYSC_DVFS_G3D) ? volt_table_g3d_v2[idx][0] : (id == SYSC_DVFS_MIF) ? volt_table_mif_v2[idx][0] : (id == SYSC_DVFS_INT) ? volt_table_int_v2[idx][0] : (id == SYSC_DVFS_CAM) ? volt_table_cam_v2[idx][0] : 0); } else if (cal_get_table_ver() <= 8) { /* table ver 6, 7, 8 */ freq = ((id == SYSC_DVFS_BIG) ? volt_table_big_v3[idx][0] : (id == SYSC_DVFS_LIT) ? volt_table_lit_v3[idx][0] : (id == SYSC_DVFS_G3D) ? volt_table_g3d_v3[idx][0] : (id == SYSC_DVFS_MIF) ? volt_table_mif_v3[idx][0] : (id == SYSC_DVFS_INT) ? volt_table_int_v3[idx][0] : (id == SYSC_DVFS_CAM) ? volt_table_cam_v3[idx][0] : 0); } return freq; }
int gpu_dvfs_decide_max_clock(struct exynos_context *platform) { if (!platform) return -1; if (cal_get_table_ver() == 12) platform->gpu_max_clock = platform->table[GPU_L2].clock; return 0; }
u32 cal_get_volt(u32 id, s32 level) { u32 volt; u32 asvgrp; u32 minlvl = cal_get_min_lv(id); const u32 *p_table; u32 idx; Assert(level >= 0); Assert(id<SYSC_DVFS_NUM); if (level >= minlvl) level = minlvl; idx = level; if (cal_get_table_ver() <= 1) { p_table = ((id == SYSC_DVFS_CL0) ? volt_table_cpu[idx] : (id == SYSC_DVFS_G3D) ? volt_table_g3d[idx] : (id == SYSC_DVFS_MIF) ? volt_table_mif[idx] : volt_table_int[idx]); } else { p_table = ((id == SYSC_DVFS_CL0) ? volt_table_cpu_V02[idx] : (id == SYSC_DVFS_G3D) ? volt_table_g3d_V02[idx] : (id == SYSC_DVFS_MIF) ? volt_table_mif_V02[idx] : volt_table_int_V02[idx]); } asvgrp = cal_get_asv_grp(id, level); volt = p_table[asvgrp+1]; if (cal_get_ssa_volt(id) > volt) volt = cal_get_ssa_volt(id); volt += cal_get_boost_volt(id, level); return volt; }
unsigned int exynos_get_table_ver(void) { return cal_get_table_ver(); }
u32 cal_get_abb(u32 id, s32 level) { u32 match_abb; u32 asv_grp; u32 min_lvl = cal_get_min_lv(id); u32 is_fs_abb = cal_get_fs_abb(); u32 fs_abb; const u32 *p_table = NULL; u32 idx; Assert(level >= 0); if (level >= min_lvl) level = min_lvl; idx = level; if (cal_get_table_ver() == 0) { p_table = ((id == SYSC_DVFS_BIG) ? abb_table_big_v0[idx] : (id == SYSC_DVFS_LIT) ? abb_table_lit_v0[idx] : (id == SYSC_DVFS_G3D) ? abb_table_g3d_v0[idx] : (id == SYSC_DVFS_MIF) ? abb_table_mif_v0[idx] : (id == SYSC_DVFS_INT) ? abb_table_int_v0[idx] : NULL); } else if (cal_get_table_ver() <= 4) { p_table = ((id == SYSC_DVFS_BIG) ? abb_table_big_v1[idx] : (id == SYSC_DVFS_LIT) ? abb_table_lit_v1[idx] : (id == SYSC_DVFS_G3D) ? abb_table_g3d_v1[idx] : (id == SYSC_DVFS_MIF) ? abb_table_mif_v1[idx] : (id == SYSC_DVFS_INT) ? abb_table_int_v1[idx] : NULL); } else if (cal_get_table_ver() == 5) { p_table = ((id == SYSC_DVFS_BIG) ? abb_table_big_v2[idx] : (id == SYSC_DVFS_LIT) ? abb_table_lit_v2[idx] : (id == SYSC_DVFS_G3D) ? abb_table_g3d_v2[idx] : (id == SYSC_DVFS_MIF) ? abb_table_mif_v2[idx] : (id == SYSC_DVFS_INT) ? abb_table_int_v2[idx] : NULL); } else if (cal_get_table_ver() <= 8) { p_table = ((id == SYSC_DVFS_BIG) ? abb_table_big_v3[idx] : (id == SYSC_DVFS_LIT) ? abb_table_lit_v3[idx] : (id == SYSC_DVFS_G3D) ? abb_table_g3d_v3[idx] : (id == SYSC_DVFS_MIF) ? abb_table_mif_v3[idx] : (id == SYSC_DVFS_INT) ? abb_table_int_v3[idx] : NULL); } Assert(p_table != NULL); if (p_table == NULL) return 0; if (is_fs_abb) { if (id == SYSC_DVFS_BIG) fs_abb = GetBits(CHIPID_ASV_TBL_BASE + 0x0010, 0, 0xF); else if (id == SYSC_DVFS_LIT) fs_abb = GetBits(CHIPID_ASV_TBL_BASE + 0x0010, 4, 0xF); else if (id == SYSC_DVFS_G3D) fs_abb = GetBits(CHIPID_ASV_TBL_BASE + 0x0010, 8, 0xF); else if (id == SYSC_DVFS_MIF) fs_abb = GetBits(CHIPID_ASV_TBL_BASE + 0x0010, 12, 0xF); else if (id == SYSC_DVFS_INT) fs_abb = GetBits(CHIPID_ASV_TBL_BASE + 0x0010, 16, 0xF); else fs_abb = ABB_BYPASS; match_abb = fs_abb; } else { asv_grp = cal_get_asv_grp(id, level); match_abb = p_table[asv_grp + 1]; } return match_abb; }
u32 cal_get_volt(u32 id, s32 level) { u32 volt, lock_volt; u32 asvgrp; u32 minlvl = cal_get_min_lv(id); const u32 *p_table = NULL; u32 idx; Assert(level >= 0); if (level >= minlvl) level = minlvl; idx = level; if (cal_get_table_ver() == 0) { p_table = ((id == SYSC_DVFS_BIG) ? volt_table_big_v0[idx] : (id == SYSC_DVFS_LIT) ? volt_table_lit_v0[idx] : (id == SYSC_DVFS_G3D) ? volt_table_g3d_v0[idx] : (id == SYSC_DVFS_MIF) ? volt_table_mif_v0[idx] : (id == SYSC_DVFS_INT) ? volt_table_int_v0[idx] : (id == SYSC_DVFS_CAM) ? volt_table_cam_v0[idx] : NULL); Assert(p_table != NULL); } else if (cal_get_table_ver() <= 4) { /* table ver 1, 2, 3, 4 */ p_table = ((id == SYSC_DVFS_BIG) ? volt_table_big_v1[idx] : (id == SYSC_DVFS_LIT) ? volt_table_lit_v1[idx] : (id == SYSC_DVFS_G3D) ? volt_table_g3d_v1[idx] : (id == SYSC_DVFS_MIF) ? volt_table_mif_v1[idx] : (id == SYSC_DVFS_INT) ? volt_table_int_v1[idx] : (id == SYSC_DVFS_CAM) ? volt_table_cam_v1[idx] : NULL); Assert(p_table != NULL); } else if (cal_get_table_ver() == 5) { /* table ver 5 */ p_table = ((id == SYSC_DVFS_BIG) ? volt_table_big_v2[idx] : (id == SYSC_DVFS_LIT) ? volt_table_lit_v2[idx] : (id == SYSC_DVFS_G3D) ? volt_table_g3d_v2[idx] : (id == SYSC_DVFS_MIF) ? volt_table_mif_v2[idx] : (id == SYSC_DVFS_INT) ? volt_table_int_v2[idx] : (id == SYSC_DVFS_CAM) ? volt_table_cam_v2[idx] : NULL); Assert(p_table != NULL); } else if (cal_get_table_ver() <= 8) { /* table ver 6, 7, 8 */ p_table = ((id == SYSC_DVFS_BIG) ? volt_table_big_v3[idx] : (id == SYSC_DVFS_LIT) ? volt_table_lit_v3[idx] : (id == SYSC_DVFS_G3D) ? volt_table_g3d_v3[idx] : (id == SYSC_DVFS_MIF) ? volt_table_mif_v3[idx] : (id == SYSC_DVFS_INT) ? volt_table_int_v3[idx] : (id == SYSC_DVFS_CAM) ? volt_table_cam_v3[idx] : NULL); Assert(p_table != NULL); } if (p_table == NULL) return 0; asvgrp = cal_get_asv_grp(id, level); volt = p_table[asvgrp + 1]; lock_volt = cal_get_lock_volt(id); if (lock_volt > volt) volt = lock_volt; return volt; }