void __init h8300_timer_setup(void)
{
unsigned int div;
unsigned int cnt;
calc_param(cnt, div, divide_rate, 0x10000);
setup_irq(_16IRQ, &timer16_irq);
/* initalize timer */
ctrl_outb(0, TSTR);
ctrl_outb(CCLR0 | div, _16BASE + TCR);
ctrl_outw(cnt, _16BASE + GRA);
ctrl_bset(4 + CONFIG_H8300_TIMER16_CH, TISRA);
ctrl_bset(CONFIG_H8300_TIMER16_CH, TSTR);
}
void __init h8300_timer_setup(void)
{
unsigned int div;
unsigned int cnt;
calc_param(cnt, div, divide_rate, 0x10000);
setup_irq(ITUIRQ, &itu_irq);
/* initalize timer */
ctrl_outb(0, TSTR);
ctrl_outb(CCLR0 | div, ITUBASE + TCR);
ctrl_outb(0x01, ITUBASE + TIER);
ctrl_outw(cnt, ITUBASE + GRA);
ctrl_bset(CONFIG_H8300_ITU_CH, TSTR);
}
void __init h8300_timer_setup(void)
{
unsigned int cnt;
unsigned int div;
calc_param(cnt, div, divide_rate, 0x10000);
setup_irq(TPUIRQ, &tpu_irq);
/* TPU module enabled */
ctrl_bclr(3, MSTPCRH);
ctrl_outb(0, TSTR);
ctrl_outb(CCLR0 | div, TPUBASE + _TCR);
ctrl_outb(0, TPUBASE + _TMDR);
ctrl_outw(0, TPUBASE + _TIOR);
ctrl_outb(0x01, TPUBASE + _TIER);
ctrl_outw(cnt, TPUBASE + _GRA);
ctrl_bset(CONFIG_H8300_TPU_CH, TSTR);
}
void __init h8300_timer_setup(void)
{
unsigned int div;
unsigned int cnt;
calc_param(cnt, div, divide_rate, 0x10000);
div++;
setup_irq(_8IRQ, &timer8_irq);
#if defined(CONFIG_CPU_H8S)
/* Timer module enable */
ctrl_bclr(0, MSTPCRL)
#endif
/* initalize timer */
ctrl_outw(cnt, _8BASE + TCORA);
ctrl_outw(0x0000, _8BASE + _8TCSR);
ctrl_outw((CMIEA|CCLR_CMA|CKS2) << 8 | div,
_8BASE + _8TCR);
}