//--------------------------------------------------------------------
void
ccreg(char *in)
{
uint8_t hb, out, addr;
if(in[1] == 'w' && fromhex(in+2, &addr, 1) && fromhex(in+4, &hb, 1)) {
cc1100_writeReg(addr, hb);
ccStrobe( CC1100_SCAL );
ccRX();
DH2(addr); DH2(hb); DNL();
} else if(fromhex(in+1, &hb, 1)) {
if(hb == 0x99) {
for(uint8_t i = 0; i < 0x30; i++) {
DH2(cc1100_readReg(i));
if((i&7) == 7)
DNL();
}
} else {
out = cc1100_readReg(hb);
DC('C'); // prefix
DH2(hb); // register number
DS_P( PSTR(" = ") );
DH2(out); // result, hex
DS_P( PSTR(" / ") );
DU(out,2); // result, decimal
DNL();
}
}
}
void native_init(uint8_t mode) {
EIMSK &= ~_BV(CC1100_INT); // disable INT - we'll poll...
SET_BIT( CC1100_CS_DDR, CC1100_CS_PIN ); // CS as output
native_on = 0;
CC1100_DEASSERT; // Toggle chip select signal
my_delay_us(30);
CC1100_ASSERT;
my_delay_us(30);
CC1100_DEASSERT;
my_delay_us(45);
ccStrobe( CC1100_SRES ); // Send SRES command
my_delay_us(100);
if (!mode || mode>MAX_MODES)
return;
// load configuration
for (uint8_t i = 0; i<60; i += 2) {
if (pgm_read_byte( &NATIVE_CFG[i] )>0x40)
break;
cc1100_writeReg( pgm_read_byte(&NATIVE_CFG[i]),
pgm_read_byte(&NATIVE_CFG[i+1]) );
}
// load special configuration
for (uint8_t i = 0; i<20; i += 2) {
if (pgm_read_byte( &MODE_CFG[mode-1][i] )>0x40)
break;
cc1100_writeReg( pgm_read_byte(&MODE_CFG[mode-1][i]),
pgm_read_byte(&MODE_CFG[mode-1][i+1]) );
}
ccStrobe( CC1100_SCAL );
native_on = mode;
checkFrequency();
my_delay_ms(1);
}
void
rf_asksin_init(void)
{
#ifdef ARM
#ifndef CC_ID
AT91C_BASE_AIC->AIC_IDCR = 1 << CC1100_IN_PIO_ID; // disable INT - we'll poll...
#endif
CC1100_CS_BASE->PIO_PPUER = _BV(CC1100_CS_PIN); //Enable pullup
CC1100_CS_BASE->PIO_OER = _BV(CC1100_CS_PIN); //Enable output
CC1100_CS_BASE->PIO_PER = _BV(CC1100_CS_PIN); //Enable PIO control
#else
EIMSK &= ~_BV(CC1100_INT); // disable INT - we'll poll...
SET_BIT( CC1100_CS_DDR, CC1100_CS_PIN ); // CS as output
#endif
CC1100_DEASSERT; // Toggle chip select signal
my_delay_us(30);
CC1100_ASSERT;
my_delay_us(30);
CC1100_DEASSERT;
my_delay_us(45);
CCSTROBE( CC1100_SRES ); // Send SRES command
my_delay_us(100);
#ifdef CC_ID
CC1100_ASSERT;
uint8_t *cfg = EE_CC1100_CFG;
for(uint8_t i = 0; i < EE_CC1100_CFG_SIZE; i++) {
cc1100_sendbyte(erb(cfg++));
}
CC1100_DEASSERT;
uint8_t *pa = EE_CC1100_PA;
CC1100_ASSERT; // setup PA table
cc1100_sendbyte( CC1100_PATABLE | CC1100_WRITE_BURST );
for (uint8_t i = 0;i<8;i++) {
cc1100_sendbyte(erb(pa++));
}
CC1100_DEASSERT;
#endif
// load configuration
for (uint8_t i = 0; i < sizeof(ASKSIN_CFG); i += 2) {
CC1100_WRITEREG( pgm_read_byte(&ASKSIN_CFG[i]),
pgm_read_byte(&ASKSIN_CFG[i+1]) );
}
#ifdef HAS_ASKSIN_FUP
if (asksin_update_mode) {
for (uint8_t i = 0; i < sizeof(ASKSIN_UPDATE_CFG); i += 2) {
cc1100_writeReg( pgm_read_byte(&ASKSIN_UPDATE_CFG[i]),
pgm_read_byte(&ASKSIN_UPDATE_CFG[i+1]) );
}
}
#endif
CCSTROBE( CC1100_SCAL );
my_delay_ms(4);
// enable RX, but don't enable the interrupt
do {
CCSTROBE(CC1100_SRX);
} while (CC1100_READREG(CC1100_MARCSTATE) != MARCSTATE_RX);
}
