uint8_t setup_cc2500(void) {
uint8_t returnValue=0;
uint8_t initial_power = 0xFB; // 0 dBm
// Set-up rx_callback function
do
{
// Changed
//spi_init(); // Initialize SPI port
// FIXME Add uscib0 files
cc_powerup_reset(); // Reset CCxxxx
// TODO implement this
wait_cycles(500); // Wait for device to reset (Not sure why this is needed)
if(writeRFSettings()) // Write RF settings to config reg
{
returnValue = 1; // Failed
break;
}
// FIXME Add uscib0 files
cc_write_burst_reg( TI_CCxxx0_PATABLE, &initial_power, 1);//Write PATABLE
// FIXME Add uscib0 files
cc_strobe(TI_CCxxx0_SIDLE);
WAIT1_Waitms(10);
cc_strobe(TI_CCxxx0_SFRX); // Flush RXFIFO
WAIT1_Waitms(10);
cc_strobe(TI_CCxxx0_SFTX); // Flush RXFIFO
WAIT1_Waitms(10);
cc_strobe(TI_CCxxx0_SRX); // Initialize CCxxxx in RX mode.
returnValue = cc_read_status(TI_CCxxx0_MARCSTATE);
returnValue =0;
// When a pkt is received, it will
// signal on GDO0 and wake CPU
// FIXME
// Configure GDO0 port
// GDO0_PxIES |= GDO0_PIN; // Int on falling edge (end of pkt)
// GDO0_PxIFG &= ~GDO0_PIN; // Clear flag
// GDO0_PxIE |= GDO0_PIN; // Enable int on end of packet
CC_2500_SETUP_DONE = true;
}while(0);
return returnValue;
}
/*******************************************************************************
* @fn cc2500_sleep( );
* @brief Set device to low power sleep mode
* ****************************************************************************/
void cc2500_sleep( )
{
// Set device to idle
cc_strobe(TI_CCxxx0_SIDLE);
// Set device to power-down (sleep) mode
cc_strobe(TI_CCxxx0_SPWD);
}
void Quick_Reset_Core()
{
cc_strobe(TI_CCxxx0_SIDLE);
WAIT1_WaitCycles(1000);
cc_strobe(TI_CCxxx0_SFRX); // Flush RXFIFO
WAIT1_WaitCycles(1000);
cc_strobe(TI_CCxxx0_SFTX); // Flush RXFIFO
WAIT1_WaitCycles(1000);
cc_strobe(TI_CCxxx0_SRX); // Initialize CCxxxx in RX mode.
}
/*******************************************************************************
* @fn void setup_radio( uint8_t (*callback)(void) )
* @brief Initialize radio and register Rx Callback function
* ****************************************************************************/
void setup_cc2500( uint8_t (*callback)(uint8_t*, uint8_t) )
{
uint8_t initial_power = 0xFB; // 0 dBm
// Set-up rx_callback function
rx_callback = callback;
spi_setup(); // Initialize SPI port
cc_powerup_reset(); // Reset CCxxxx
wait_cycles(500); // Wait for device to reset (Not sure why this is needed)
writeRFSettings(); // Write RF settings to config reg
cc_write_burst_reg( TI_CCxxx0_PATABLE, &initial_power, 1);//Write PATABLE
cc_strobe(TI_CCxxx0_SRX); // Initialize CCxxxx in RX mode.
// When a pkt is received, it will
// signal on GDO0 and wake CPU
// Configure GDO0 port
GDO0_PxIES |= GDO0_PIN; // Int on falling edge (end of pkt)
GDO0_PxIFG &= ~GDO0_PIN; // Clear flag
GDO0_PxIE |= GDO0_PIN; // Enable int on end of packet
}
/*******************************************************************************
* @fn cc2500_tx( uint8_t* p_buffer, uint8_t length )
* @brief Send raw message through radio
* ****************************************************************************/
void cc2500_tx( uint8_t* p_buffer, uint8_t length )
{
volatile int i;
// GDO0_PxIE &= ~GDO0_PIN;
// Disable interrupt
//PORT_PDD_SetPinInterruptConfiguration(PTD_DEVICE, GDO0_PIN, PORT_PDD_INTERRUPT_DMA_DISABLED);
//PORT_PDD_SetPinInterruptConfiguration(PORTD_BASE_PTR,GDO0_PIN, PORT_PDD_INTERRUPT_DMA_DISABLED);
cc_write_burst_reg(TI_CCxxx0_TXFIFO, p_buffer, length); // Write TX data
cc_strobe(TI_CCxxx0_STX); // Change state to TX, initiating
// data transfer
// sometimes the chip hangs on while(!(GDO0_PxIN&GDO0_PIN)); line, see http://alvarop.com/2011/12/cc2500-project-part-1/#comment-467755523
//for (i=0;i<10000 && !(GDO0_PxIN&GDO0_PIN);i++); // Wait GDO0 to go hi or timeout -> sync TX'ed
// for (i=0;i<10000 && (GDO0_PxIN&GDO0_PIN);i++); // Wait GDO0 to clear or timeout -> end of pkt
//no used anymore
// while (!(GDO0_PxIN&GDO0_PIN));
// Wait GDO0 to go hi -> sync TX'ed
// while (GDO0_PxIN&GDO0_PIN);
// Wait GDO0 to clear -> end of pkt
// GDO0_PxIFG &= ~GDO0_PIN; // After pkt TX, this flag is set.
// // Has to be cleared before existing
//
// GDO0_PxIFG &= ~GDO0_PIN;
// Clear flag
//PORT_PDD_ClearInterruptFlags(PORTD_BASE_PTR, GDO0_PIN);
//PORT_PDD_SetPinInterruptConfiguration(PORTD_BASE_PTR, GDO0_PIN, PORT_PDD_INTERRUPT_ON_FALLING);
// GDO0_PxIE |= GDO0_PIN; // Enable interrupt
}
/*******************************************************************************
* @fn uint8_t receive_packet( uint8_t* p_buffer, uint8_t* length )
* @brief Receive packet from the radio using CC2500
* ****************************************************************************/
uint8_t receive_packet( uint8_t* p_buffer, uint8_t* length )
{
uint8_t status[2];
uint8_t packet_length;
volatile uint8_t Testo = 0;
volatile uint8_t ReadStatusValue =0;
ReadStatusValue = cc_read_status( TI_CCxxx0_RXBYTES );
// Make sure there are bytes to be read in the FIFO buffer
if ( (ReadStatusValue & TI_CCxxx0_NUM_RXBYTES ) )
{
// Read the first byte which contains the packet length
packet_length = cc_read_reg( TI_CCxxx0_RXFIFO );
// Make sure the packet length is smaller than our buffer
if ( packet_length <= *length )
{
// Read the rest of the packet
cc_read_burst_reg( TI_CCxxx0_RXFIFO, p_buffer, packet_length );
// Return packet size in length variable
*length = packet_length;
// Read two byte status
cc_read_burst_reg( TI_CCxxx0_RXFIFO, status, 2 );
// Append status bytes to buffer
memcpy( &p_buffer[packet_length], status, 2 );
// Return 1 when CRC matches, 0 otherwise
return ( status[TI_CCxxx0_LQI_RX] & TI_CCxxx0_CRC_OK );
}
else
{
// If the packet is larger than the buffer, flush the RX FIFO
*length = packet_length;
// Flush RX FIFO
cc_strobe(TI_CCxxx0_SFRX); // Flush RXFIFO
return 0;
}
}
return 0;
}
/*******************************************************************************
* @fn cc2500_tx( uint8_t* p_buffer, uint8_t length )
* @brief Send raw message through radio
* ****************************************************************************/
void cc2500_tx( uint8_t* p_buffer, uint8_t length )
{
GDO0_PxIE &= ~GDO0_PIN; // Disable interrupt
cc_write_burst_reg(TI_CCxxx0_TXFIFO, p_buffer, length); // Write TX data
cc_strobe(TI_CCxxx0_STX); // Change state to TX, initiating
// data transfer
while (!(GDO0_PxIN&GDO0_PIN));
// Wait GDO0 to go hi -> sync TX'ed
while (GDO0_PxIN&GDO0_PIN);
// Wait GDO0 to clear -> end of pkt
GDO0_PxIFG &= ~GDO0_PIN; // After pkt TX, this flag is set.
// Has to be cleared before existing
GDO0_PxIFG &= ~GDO0_PIN; // Clear flag
GDO0_PxIE |= GDO0_PIN; // Enable interrupt
}
