/* Boot the current CPU */
void start_secondary(unsigned long boot_phys_offset,
unsigned long fdt_paddr,
unsigned long hwid)
{
unsigned int cpuid = init_data.cpuid;
memset(get_cpu_info(), 0, sizeof (struct cpu_info));
set_processor_id(cpuid);
identify_cpu(¤t_cpu_data);
init_traps();
mmu_init_secondary_cpu();
gic_init_secondary_cpu();
init_secondary_IRQ();
init_maintenance_interrupt();
init_timer_interrupt();
set_current(idle_vcpu[cpuid]);
setup_cpu_sibling_map(cpuid);
/* Run local notifiers */
notify_cpu_starting(cpuid);
/*
* Ensure that previous writes are visible before marking the cpu as
* online.
*/
smp_wmb();
/* Now report this CPU is up */
cpumask_set_cpu(cpuid, &cpu_online_map);
local_irq_enable();
local_abort_enable();
check_local_cpu_errata();
printk(XENLOG_DEBUG "CPU %u booted.\n", smp_processor_id());
startup_cpu_idle_loop();
}
static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
{
info->reg_cntfrq = arch_timer_get_cntfrq();
info->reg_ctr = read_cpuid_cachetype();
info->reg_dczid = read_cpuid(DCZID_EL0);
info->reg_midr = read_cpuid_id();
info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
/* Update the 32bit ID registers only if AArch32 is implemented */
if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
}
cpuinfo_detect_icache_policy(info);
check_local_cpu_errata();
}
static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
{
info->reg_cntfrq = arch_timer_get_cntfrq();
info->reg_ctr = read_cpuid_cachetype();
info->reg_dczid = read_cpuid(DCZID_EL0);
info->reg_midr = read_cpuid_id();
info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
cpuinfo_detect_icache_policy(info);
check_local_cpu_errata();
}
static void __init processor_id(void)
{
const char *implementer = "Unknown";
struct cpuinfo_arm *c = &boot_cpu_data;
identify_cpu(c);
current_cpu_data = *c;
if ( c->midr.implementer < ARRAY_SIZE(processor_implementers) &&
processor_implementers[c->midr.implementer] )
implementer = processor_implementers[c->midr.implementer];
if ( c->midr.architecture != 0xf )
printk("Huh, cpu architecture %x, expected 0xf (defined by cpuid)\n",
c->midr.architecture);
printk("Processor: %08"PRIx32": \"%s\", variant: 0x%x, part 0x%03x, rev 0x%x\n",
c->midr.bits, implementer,
c->midr.variant, c->midr.part_number, c->midr.revision);
#if defined(CONFIG_ARM_64)
printk("64-bit Execution:\n");
printk(" Processor Features: %016"PRIx64" %016"PRIx64"\n",
boot_cpu_data.pfr64.bits[0], boot_cpu_data.pfr64.bits[1]);
printk(" Exception Levels: EL3:%s EL2:%s EL1:%s EL0:%s\n",
cpu_has_el3_32 ? "64+32" : cpu_has_el3_64 ? "64" : "No",
cpu_has_el2_32 ? "64+32" : cpu_has_el2_64 ? "64" : "No",
cpu_has_el1_32 ? "64+32" : cpu_has_el1_64 ? "64" : "No",
cpu_has_el0_32 ? "64+32" : cpu_has_el0_64 ? "64" : "No");
printk(" Extensions:%s%s%s\n",
cpu_has_fp ? " FloatingPoint" : "",
cpu_has_simd ? " AdvancedSIMD" : "",
cpu_has_gicv3 ? " GICv3-SysReg" : "");
printk(" Debug Features: %016"PRIx64" %016"PRIx64"\n",
boot_cpu_data.dbg64.bits[0], boot_cpu_data.dbg64.bits[1]);
printk(" Auxiliary Features: %016"PRIx64" %016"PRIx64"\n",
boot_cpu_data.aux64.bits[0], boot_cpu_data.aux64.bits[1]);
printk(" Memory Model Features: %016"PRIx64" %016"PRIx64"\n",
boot_cpu_data.mm64.bits[0], boot_cpu_data.mm64.bits[1]);
printk(" ISA Features: %016"PRIx64" %016"PRIx64"\n",
boot_cpu_data.isa64.bits[0], boot_cpu_data.isa64.bits[1]);
#endif
/*
* On AArch64 these refer to the capabilities when running in
* AArch32 mode.
*/
if ( cpu_has_aarch32 )
{
printk("32-bit Execution:\n");
printk(" Processor Features: %08"PRIx32":%08"PRIx32"\n",
boot_cpu_data.pfr32.bits[0], boot_cpu_data.pfr32.bits[1]);
printk(" Instruction Sets:%s%s%s%s%s%s\n",
cpu_has_aarch32 ? " AArch32" : "",
cpu_has_arm ? " A32" : "",
cpu_has_thumb ? " Thumb" : "",
cpu_has_thumb2 ? " Thumb-2" : "",
cpu_has_thumbee ? " ThumbEE" : "",
cpu_has_jazelle ? " Jazelle" : "");
printk(" Extensions:%s%s\n",
cpu_has_gentimer ? " GenericTimer" : "",
cpu_has_security ? " Security" : "");
printk(" Debug Features: %08"PRIx32"\n",
boot_cpu_data.dbg32.bits[0]);
printk(" Auxiliary Features: %08"PRIx32"\n",
boot_cpu_data.aux32.bits[0]);
printk(" Memory Model Features: "
"%08"PRIx32" %08"PRIx32" %08"PRIx32" %08"PRIx32"\n",
boot_cpu_data.mm32.bits[0], boot_cpu_data.mm32.bits[1],
boot_cpu_data.mm32.bits[2], boot_cpu_data.mm32.bits[3]);
printk(" ISA Features: %08x %08x %08x %08x %08x %08x\n",
boot_cpu_data.isa32.bits[0], boot_cpu_data.isa32.bits[1],
boot_cpu_data.isa32.bits[2], boot_cpu_data.isa32.bits[3],
boot_cpu_data.isa32.bits[4], boot_cpu_data.isa32.bits[5]);
}
else
{
printk("32-bit Execution: Unsupported\n");
}
processor_setup();
check_local_cpu_errata();
}
