void DSPHINT(void) { register pcm_more_callback_type get_more; /* No stack for this */ unsigned int i; IO_INTC_FIQ0 = 1 << 11; switch (dsp_message.msg) { case MSG_DEBUGF: /* DSP stores one character per word. */ for (i = 0; i < sizeof(buffer); i++) { buffer[i] = dsp_message.payload.debugf.buffer[i]; } DEBUGF("DSP: %s", buffer); break; case MSG_REFILL: /* Buffer empty. Try to get more. */ get_more = pcm_callback_for_more; size = 0; if (get_more == NULL || (get_more(&start, &size), size == 0)) { /* Callback missing or no more DMA to do */ pcm_play_dma_stop(); pcm_play_dma_stopped_callback(); } { unsigned long sdem_addr=(unsigned long)start - CONFIG_SDRAM_START; /* Flush any pending cache writes */ clean_dcache_range(start, size); /* set the new DMA values */ DSP_(_sdem_addrl) = sdem_addr & 0xffff; DSP_(_sdem_addrh) = sdem_addr >> 16; DSP_(_sdem_dsp_size) = size; DEBUGF("pcm_sdram at 0x%08lx, sdem_addr 0x%08lx", (unsigned long)start, (unsigned long)sdem_addr); } break; default: DEBUGF("DSP: unknown msg 0x%04x", dsp_message.msg); break; } /* Re-Activate the channel */ dsp_wake(); DEBUGF("DSP: %s", buffer); }
/*---------------------------------------------------------------------------+ * program_ecc. *---------------------------------------------------------------------------*/ static void program_ecc(unsigned long start_address, unsigned long num_bytes) { u32 val; char str[] = "ECC generation -"; #if defined(CONFIG_PRAM) u32 *magicPtr; u32 magic; if ((mfspr(SPRN_DBCR0) & 0x80000000) == 0) { /* only if no external debugger is alive! * Check whether vxWorks is using EDR logging, if yes zero * also PostMortem and user reserved memory */ magicPtr = (u32 *)(start_address + num_bytes - (CONFIG_PRAM*1024) + sizeof(u32)); magic = in_be32(magicPtr); debug("%s: CONFIG_PRAM %d kB magic 0x%x 0x%p\n", __FUNCTION__, CONFIG_PRAM, magicPtr, magic); if (magic == 0xbeefbabe) { printf("%s: preserving at %p\n", __FUNCTION__, magicPtr); num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM; } } #endif sync(); puts(str); /* ECC bit set method for cached memory */ /* Fast method, no noticeable delay */ dcbz_area(start_address, num_bytes); /* Write modified dcache lines back to memory */ clean_dcache_range(start_address, start_address + num_bytes); blank_string(strlen(str)); /* Clear error status */ mfsdram(DDR0_00, val); mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); /* * Clear possible ECC errors * If not done, then we could get an interrupt later on when * exceptions are enabled. */ mtspr(SPRN_MCSR, mfspr(SPRN_MCSR)); /* Set 'int_mask' parameter to functionnal value */ mfsdram(DDR0_01, val); mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF)); return; }
static void program_ecc(u32 start_address, u32 num_bytes, u32 tlb_word2_i_value) { u32 val; u32 current_addr = start_address; u32 size; int bytes_remaining; sync(); wait_ddr_idle(); /* * Because of 440EPx errata CHIP 11, we don't touch the last 256 * bytes of SDRAM. */ bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE; /* * We have to write the ECC bytes by zeroing and flushing in smaller * steps, since the whole 256MByte takes too long for the external * watchdog. */ while (bytes_remaining > 0) { size = min((64 << 20), bytes_remaining); /* Write zero's to SDRAM */ dcbz_area(current_addr, size); /* Write modified dcache lines back to memory */ clean_dcache_range(current_addr, current_addr + size); current_addr += 64 << 20; bytes_remaining -= 64 << 20; WATCHDOG_RESET(); } sync(); wait_ddr_idle(); /* Clear error status */ mfsdram(DDR0_00, val); mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); /* Set 'int_mask' parameter to functionnal value */ mfsdram(DDR0_01, val); mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF)); sync(); wait_ddr_idle(); }
void bl2_platform_setup(void) { dw_mmc_params_t params; struct mmc_device_info info; hikey_sp804_init(); hikey_gpio_init(); hikey_pmussi_init(); hikey_hi6553_init(); /* Clear SRAM since it'll be used by MCU right now. */ memset((void *)SRAM_BASE, 0, SRAM_SIZE); dsb(); hikey_ddr_init(DDR_FREQ_800M); hikey_security_setup(); hikey_boardid_init(); init_acpu_dvfs(); hikey_rtc_init(); hikey_sd_init(); hikey_jumper_init(); hikey_mmc_pll_init(); /* Clean SRAM before MCU used */ clean_dcache_range(SRAM_BASE, SRAM_SIZE); reset_dwmmc_clk(); memset(¶ms, 0, sizeof(dw_mmc_params_t)); params.reg_base = DWMMC0_BASE; params.desc_base = HIKEY_MMC_DESC_BASE; params.desc_size = 1 << 20; params.clk_rate = 24 * 1000 * 1000; params.bus_width = MMC_BUS_WIDTH_8; params.flags = MMC_FLAG_CMD23; info.mmc_dev_type = MMC_IS_EMMC; dw_mmc_init(¶ms, &info); hikey_io_setup(); }
int32_t tegra_soc_validate_power_state(unsigned int power_state, psci_power_state_t *req_state) { int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; int cpu = plat_my_core_pos(); /* save the core wake time (in TSC ticks)*/ percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) << TEGRA186_WAKE_TIME_SHIFT; /* * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that * the correct value is read in tegra_soc_pwr_domain_suspend(), which * is called with caches disabled. It is possible to read a stale value * from DRAM in that function, because the L2 cache is not flushed * unless the cluster is entering CC6/CC7. */ clean_dcache_range((uint64_t)&percpu_data[cpu], sizeof(percpu_data[cpu])); /* Sanity check the requested state id */ switch (state_id) { case PSTATE_ID_CORE_IDLE: case PSTATE_ID_CORE_POWERDN: /* Core powerdown request */ req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; break; default: ERROR("%s: unsupported state id (%d)\n", __func__, state_id); return PSCI_E_INVALID_PARAMS; } return PSCI_E_SUCCESS; }
/*----------------------------------------------------------------------------- * Function: initdram * Description: Configures SDRAM memory banks for DDR operation. * Auto Memory Configuration option reads the DDR SDRAM EEPROMs * via the IIC bus and then configures the DDR SDRAM memory * banks appropriately. If Auto Memory Configuration is * not used, it is assumed that no DIMM is plugged *-----------------------------------------------------------------------------*/ phys_size_t initdram(int board_type) { unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; unsigned long dimm_ranks[MAXDIMMS]; unsigned long ranks; unsigned long rows; unsigned long banks; unsigned long cols; unsigned long width; unsigned long const sdram_freq = get_bus_freq(0); unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr); /* on board dimm banks */ unsigned long cas_latency = 0; /* to quiet initialization warning */ unsigned long dram_size; debug("\nEntering initdram()\n"); /*------------------------------------------------------------------ * Stop the DDR-SDRAM controller. *-----------------------------------------------------------------*/ mtsdram(DDR0_02, DDR0_02_START_ENCODE(0)); /* * Make sure I2C controller is initialized * before continuing. */ /* switch to correct I2C bus */ I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /*------------------------------------------------------------------ * Clear out the serial presence detect buffers. * Perform IIC reads from the dimm. Fill in the spds. * Check to see if the dimm slots are populated *-----------------------------------------------------------------*/ get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks); /*------------------------------------------------------------------ * Check the frequency supported for the dimms plugged. *-----------------------------------------------------------------*/ check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); /*------------------------------------------------------------------ * Check and get size information. *-----------------------------------------------------------------*/ get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks, &cols, &width); /*------------------------------------------------------------------ * Check the voltage type for the dimms plugged. *-----------------------------------------------------------------*/ check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks); /*------------------------------------------------------------------ * Program registers for SDRAM controller. *-----------------------------------------------------------------*/ mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) | DDR0_00_DLL_START_POINT_DECODE(0x0A)); mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) | DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) | DDR0_01_INT_MASK_ENCODE(0xFF)); program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, rows, &cas_latency); program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); /* * TODO: tFAW not found in SPD. Value of 13 taken from Sequoia * board SDRAM, but may be overly conservative. */ mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) | DDR0_07_TFAW_ENCODE(13) | DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) | DDR0_07_AREFRESH_ENCODE(0)); mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) | DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) | DDR0_08_DDRII_ENCODE(1)); mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) | DDR0_09_RTT_0_ENCODE(0x1) | DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) | DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20)); program_ddr0_10(dimm_ranks, ranks); program_ddr0_11(sdram_freq); mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3)); mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) | DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) | DDR0_14_REG_DIMM_ENABLE_ENCODE(0)); mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY)); mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) | DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) | DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) | DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY)); mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) | DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) | DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) | DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY)); mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) | DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) | DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) | DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS)); mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) | DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) | DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) | DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS)); program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width); mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) | DDR0_23_FWC_ENCODE(0)); program_ddr0_24(ranks); program_ddr0_26(sdram_freq); program_ddr0_27(sdram_freq); mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) | DDR0_28_EMRS2_DATA_ENCODE(0x0000)); mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000)); mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) | DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency)); program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, cols, banks); program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); denali_sdram_register_dump(); dram_size = (width >= 64) ? 8 : 4; dram_size *= 1 << cols; dram_size *= banks; dram_size *= 1 << rows; dram_size *= ranks; debug("dram_size = %lu\n", dram_size); /* Start the SDRAM controler */ mtsdram(DDR0_02, DDR0_02_START_ENCODE(1)); denali_wait_for_dlllock(); #if defined(CONFIG_DDR_DATA_EYE) /* * Map the first 1 MiB of memory in the TLB, and perform the data eye * search. */ program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE); denali_core_search_data_eye(); denali_sdram_register_dump(); remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE); #endif #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0); sync(); /* Zero the memory */ debug("Zeroing SDRAM..."); #if defined(CONFIG_SYS_MEM_TOP_HIDE) dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE); #else #error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file #endif /* Write modified dcache lines back to memory */ clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE); debug("Completed\n"); sync(); remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size); #if defined(CONFIG_DDR_ECC) /* * If ECC is enabled, clear and enable interrupts */ if (is_ecc_enabled()) { u32 val; sync(); /* Clear error status */ mfsdram(DDR0_00, val); mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); /* Set 'int_mask' parameter to functionnal value */ mfsdram(DDR0_01, val); mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF); #if defined(CONFIG_DDR_DATA_EYE) /* * Running denali_core_search_data_eye() when ECC is enabled * causes non-ECC machine checks. This clears them. */ print_mcsr(); mtspr(SPRN_MCSR, mfspr(SPRN_MCSR)); print_mcsr(); #endif sync(); } #endif /* defined(CONFIG_DDR_ECC) */ #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */ program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE); return dram_size; }
/* Helper function that cleans the data cache only if it is enabled. */ static inline __attribute__((unused)) void xlat_clean_dcache_range(uintptr_t addr, size_t size) { if (is_dcache_enabled()) clean_dcache_range(addr, size); }
static void program_ecc_addr(unsigned long start_address, unsigned long num_bytes, unsigned long tlb_word2_i_value) { unsigned long current_address; unsigned long end_address; unsigned long address_increment; unsigned long mcopt1; char str[] = "ECC generation -"; char slash[] = "\\|/-\\|/-"; int loop = 0; int loopi = 0; current_address = start_address; mfsdram(SDRAM_MCOPT1, mcopt1); if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) { mtsdram(SDRAM_MCOPT1, (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN); sync(); eieio(); wait_ddr_idle(); puts(str); #ifdef CONFIG_440 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) { #endif /* ECC bit set method for non-cached memory */ if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32) address_increment = 4; else address_increment = SDRAM_DATA_ALT_WIDTH; end_address = current_address + num_bytes; while (current_address < end_address) { *((unsigned long *)current_address) = 0; current_address += address_increment; if ((loop++ % (2 << 20)) == 0) { putc('\b'); putc(slash[loopi++ % 8]); } } #ifdef CONFIG_440 } else { /* ECC bit set method for cached memory */ dcbz_area(start_address, num_bytes); /* Write modified dcache lines back to memory */ clean_dcache_range(start_address, start_address + num_bytes); } #endif /* CONFIG_440 */ blank_string(strlen(str)); sync(); eieio(); wait_ddr_idle(); /* clear ECC error repoting registers */ mtsdram(SDRAM_ECCES, 0xffffffff); mtdcr(0x4c, 0xffffffff); mtsdram(SDRAM_MCOPT1, (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP); sync(); eieio(); wait_ddr_idle(); } }
static bool setup_channel(struct channel_control_block *ccb_p) { struct context_data context_buffer; struct channel_descriptor *cd_p; unsigned int channel_cfg; unsigned int channel; unsigned long pc; memset(&context_buffer, 0x00, sizeof (context_buffer)); channel = ccb_p - ccb_array; cd_p = ccb_p->channel_desc; /* Obtain script start address for perihperal and transfer type */ pc = get_script_pc(cd_p->per_type, cd_p->tran_type); if (pc == (unsigned short)-1) return false; /* Failed to find a script */ context_buffer.channel_state.pc = pc; if (cd_p->per_type != SDMA_PER_MEMORY && cd_p->per_type != SDMA_PER_DSP) { /* Set peripheral DMA request mask for this channel */ context_buffer.event_mask1 = 1ul << cd_p->event_id1; if (cd_p->per_type == SDMA_PER_ATA) { /* ATA has two */ context_buffer.event_mask2 = 1ul << cd_p->event_id2; } context_buffer.shp_addr = cd_p->shp_addr; context_buffer.wml = cd_p->wml; } else { context_buffer.wml = SDMA_PER_ADDR_SDRAM; } /* Send channel context to SDMA core */ clean_dcache_range(&context_buffer, sizeof (context_buffer)); sdma_write_words((unsigned long *)&context_buffer, CHANNEL_CONTEXT_ADDR(channel), sizeof (context_buffer)/4); ccb_p->status.error = 0; /* Clear channel-wide error flag */ if (cd_p->is_setup != 0) return true; /* No more to do */ /* Obtain channel ownership configuration */ channel_cfg = get_config(cd_p->tran_type); if (channel_cfg == (unsigned int)-1) return false; /* Set who owns it and thus can activate it */ set_channel_ownership(channel, channel_cfg); if (channel_cfg & CH_OWNSHP_EVT) { /* Set event ID to channel activation bitmapping */ bitset32(&SDMA_CHNENBL(cd_p->event_id1), 1ul << channel); if (cd_p->per_type == SDMA_PER_ATA) { /* ATA has two */ bitset32(&SDMA_CHNENBL(cd_p->event_id2), 1ul << channel); } } cd_p->is_setup = 1; return true; }