void fixup_irqs(void)
{
irq_cpu_offline();
clear_c0_status(ST0_IM);
}
/*
* Route interrupts to ISR(s).
*
* This function is entered with the IE disabled. It can be
* re-entered as soon as the IE is re-enabled in function
* handle_IRQ_envet().
*/
void BCMFASTPATH
plat_irq_dispatch(struct pt_regs *regs)
{
u32 pending, ipvec;
unsigned long flags = 0;
int irq;
/* Disable MIPS IRQs with pending interrupts */
pending = read_c0_cause() & CAUSEF_IP;
pending &= read_c0_status();
clear_c0_status(pending);
irq_disable_hazard();
/* Handle MIPS timer interrupt. Re-enable MIPS IRQ7
* immediately after servicing the interrupt so that
* we can take this kind of interrupt again later
* while servicing other interrupts.
*/
if (pending & CAUSEF_IP7) {
do_IRQ(7);
pending &= ~CAUSEF_IP7;
set_c0_status(STATUSF_IP7);
irq_enable_hazard();
}
/* Build bitvec for pending interrupts. Start with
* MIPS IRQ2 and add linux IRQs to higher bits to
* make the interrupt processing uniform.
*/
ipvec = pending >> CAUSEB_IP2;
if (pending & CAUSEF_IP2) {
if (ccsbr)
flags = R_REG(NULL, &ccsbr->sbflagst);
/* Read intstatus */
if (mips_corereg)
flags = R_REG(NULL, &((mips74kregs_t *)mips_corereg)->intstatus);
flags &= shints;
ipvec |= flags << SBMIPS_VIRTIRQ_BASE;
}
#ifdef CONFIG_HND_BMIPS3300_PROF
/* Handle MIPS core interrupt. Re-enable the MIPS IRQ that
* MIPS core is assigned to immediately after servicing the
* interrupt so that we can take this kind of interrupt again
* later while servicing other interrupts.
*
* mipsirq < 0 indicates MIPS core IRQ # is unknown.
*/
if (mipsirq >= 0 && (ipvec & (1 << mipsirq))) {
/* MIPS core raised the interrupt on the shared MIPS IRQ2.
* Make sure MIPS core is the only interrupt source before
* re-enabling the IRQ.
*/
if (mipsirq >= SBMIPS_VIRTIRQ_BASE) {
if (flags == (1 << (mipsirq-SBMIPS_VIRTIRQ_BASE))) {
irq = mipsirq + 2;
do_IRQ(irq);
ipvec &= ~(1 << mipsirq);
pending &= ~CAUSEF_IP2;
set_c0_status(STATUSF_IP2);
irq_enable_hazard();
}
}
/* MIPS core raised the interrupt on a dedicated MIPS IRQ.
* Re-enable the IRQ immediately.
*/
else {
irq = mipsirq + 2;
do_IRQ(irq);
ipvec &= ~(1 << mipsirq);
pending &= ~CR_IP(irq);
set_c0_status(SR_IM(irq));
irq_enable_hazard();
}
}
#endif /* CONFIG_HND_BMIPS3300_PROF */
/* Shared interrupt bits are shifted to respective bit positions in
* ipvec above. IP2 (bit 0) is of no significance, hence shifting the
* bit map by 1 to the right.
*/
ipvec >>= 1;
/* Handle all other interrupts. Re-enable disabled MIPS IRQs
* after processing all pending interrupts.
*/
for (irq = 3; ipvec != 0; irq++) {
if (ipvec & 1)
do_IRQ(irq);
ipvec >>= 1;
}
set_c0_status(pending);
irq_enable_hazard();
/* Process any pending softirqs (tasklets, softirqs ...) */
local_irq_save(flags);
if (local_softirq_pending() && !in_interrupt())
__do_softirq();
local_irq_restore(flags);
}
static inline void mask_mips_irq(struct irq_data *d)
{
clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
irq_disable_hazard();
}
static INLINE void
disable_brcm_irq(unsigned int irq)
{
clear_c0_status(SR_IM(irq));
irq_disable_hazard();
}
static inline void mask_mips_irq(unsigned int irq)
{
clear_c0_status(0x100 << (irq - mips_cpu_irq_base));
irq_disable_hazard();
}