void shiftOut(int dataPin, int clockPin, BITORDER_T bitOrder, byte value) {
CPin dat(unoPIN[dataPin]);
CPin clk(unoPIN[clockPin]);
dat.output(NOT_OPEN);
clk.output(NOT_OPEN);
for (int i = 0; i < 8; i++) {
if (bitOrder == LSBFIRST)
dat = (bit_chk(value,i)? HIGH:LOW);
else
dat = (bit_chk(value,(7-i))? HIGH:LOW);
clk = HIGH;
delayMicroseconds(2); // 2us
clk = LOW;
}
}
void ChainableLED::sendByte(byte b)
{
// Send one bit at a time, starting with the MSB
for (byte i=0; i<8; i++)
{
// If MSB is 1, write one and clock it, else write 0 and clock
if ((b & 0x80) != 0)
digitalWrite(_data_pin, HIGH);
else
digitalWrite(_data_pin, LOW);
clk();
// Advance to the next bit to send
b <<= 1;
}
}
int sc_main(int nargs, char* vargs[]){
sc_clock clk ("clk", 10, SC_NS); // ciclo de 10 ns
sc_signal <bool> res;
top principalDE("top");
principalDE.clk(clk);
principalDE.reset(res);
res.write(true); sc_start(20, SC_NS);
res.write(false); sc_start(2000000, SC_NS);
cout << endl << endl << "Programa finalizado" << endl << endl;
return 0;
}
void gpu::getClocks() {
switch (currentDriver) {
case XORG:
gpuClocksData = dXorg::getClocks();
break;
case FGLRX:
gpuClocksData = dFglrx::getClocks();
break;
case DRIVER_UNKNOWN: {
globalStuff::gpuClocksStruct clk(-1);
gpuClocksData = clk;
break;
}
}
gpuClocksDataString = convertClocks(gpuClocksData);
}
int sc_main(int argc, char* argv[])
{
sc_signal<sc_uint<4> > ain, bin, sum;
sc_signal<bool> ci,co, zflag, oflag;
sc_clock clk("clk",10,SC_NS,0.5); // Create a clock signal
sc_trace_file *fp=sc_create_vcd_trace_file("wave");
sc_trace(fp, clk, "clk");
sc_trace(fp, ain, "ain");
sc_trace(fp, bin, "bin");
sc_trace(fp, sum, "sum");
sc_trace(fp, ci, "ci");
sc_trace(fp, co, "co");
sc_trace(fp, zflag, "zflag");
sc_trace(fp, oflag, "oflag");
adder DUT("adder"); // Instantiate Device Under Test
DUT.ain(ain); // Connect ports
DUT.bin(bin);
DUT.ci(ci);
DUT.sum(sum);
DUT.co(co);
DUT.zflag(zflag);
DUT.oflag(oflag);
stim STIM("stimulus"); // Instantiate stimulus generator
STIM.clk(clk);
STIM.ain(ain);
STIM.bin(bin);
STIM.ci(ci);
check CHECK("checker"); // Instantiate checker
CHECK.clk(clk);
CHECK.ain(ain);
CHECK.bin(bin);
CHECK.ci(ci);
CHECK.sum(sum);
CHECK.co(co);
CHECK.zflag(zflag);
CHECK.oflag(oflag);
sc_start(100, SC_NS); // Run simulation
sc_close_vcd_trace_file(fp);
return 0; // Return OK, no errors.
}
void profile(OperationContext* txn, const Client& c, int op, CurOp& currentOp) {
bool tryAgain = false;
while ( 1 ) {
try {
// initialize with 1kb to start, to avoid realloc later
// doing this outside the dblock to improve performance
BufBuilder profileBufBuilder(1024);
// NOTE: It's kind of weird that we lock the op's namespace, but have to for now
// since we're sometimes inside the lock already
const string dbname(nsToDatabase(currentOp.getNS()));
scoped_ptr<Lock::DBLock> lk;
// todo: this can be slow, perhaps can re-work
if ( !txn->lockState()->isDbLockedForMode( dbname, MODE_IX ) ) {
lk.reset( new Lock::DBLock( txn->lockState(),
dbname,
tryAgain ? MODE_X : MODE_IX) );
}
Database* db = dbHolder().get(txn, dbname);
if (db != NULL) {
Lock::CollectionLock clk(txn->lockState(), db->getProfilingNS(), MODE_X);
Client::Context cx(txn, currentOp.getNS(), false);
if ( !_profile(txn, c, cx.db(), currentOp, profileBufBuilder ) && lk.get() ) {
if ( tryAgain ) {
// we couldn't profile, but that's ok, we should have logged already
break;
}
// we took an IX lock, so now we try again with an X lock
tryAgain = true;
continue;
}
}
else {
mongo::log() << "note: not profiling because db went away - "
<< "probably a close on: " << currentOp.getNS();
}
return;
}
catch (const AssertionException& assertionEx) {
warning() << "Caught Assertion while trying to profile " << opToString(op)
<< " against " << currentOp.getNS()
<< ": " << assertionEx.toString() << endl;
return;
}
}
}
int sc_main(int argc, char* argv[])
{
sc_signal<sc_int<4> > ain, bin, sum;
sc_signal<bool> ci,co;
sc_signal<bool> oflag, zflag;
sc_clock clk("clk",10,SC_NS,0.5); // Create a clock signal
adder DUT("adder"); // Instantiate Device Under Test
DUT.ain(ain); // Connect ports
DUT.bin(bin);
DUT.ci(ci);
DUT.sum(sum);
DUT.co(co);
DUT.oflag(oflag);
DUT.zflag(zflag);
stim STIM("stimulus"); // Instantiate stimulus generator
STIM.clk(clk);
STIM.ain(ain);
STIM.bin(bin);
STIM.ci(ci);
check CHECK("checker"); // Instantiate checker
CHECK.clk(clk);
CHECK.ain(ain);
CHECK.bin(bin);
CHECK.ci(ci);
CHECK.sum(sum);
CHECK.co(co);
sc_start(SC_ZERO_TIME);
sc_trace_file *tf = sc_create_vcd_trace_file("trace");
sc_trace(tf, ain, "A");
sc_trace(tf, bin, "B");
sc_trace(tf, sum, "SUM");
sc_trace(tf, ci, "CIN");
sc_trace(tf, co, "COUT");
sc_trace(tf, oflag, "OFlag");
sc_trace(tf, zflag, "ZFlag");
sc_trace(tf, clk, "CLOCK");
sc_start(10000, SC_NS);
sc_close_vcd_trace_file(tf);
return 0; // Return OK, no errors.
}
void send_message( lowlevel_unit_type &llu,
const gpb::MethodDescriptor *method,
gpb::RpcController *controller,
const gpb::Message *request,
gpb::Message *response,
gpb::Closure *done )
{
common::closure_holder done_holder(done);
common::connection_iface_sptr clk(connection_.lock( ));
if( clk.get( ) == NULL ) {
if( controller ) {
controller->SetFailed( "Connection lost" );
}
parent_->get_channel_error_callback( )( "Connection lost" );
return;
}
const rpc::options *call_opt
( get_protocol( clk ).get_method_options(method) );
if( disable_wait( ) ) {
llu.mutable_opt( )->set_wait( false );
} else {
llu.mutable_opt( )->set_wait( call_opt->wait( ) );
llu.mutable_opt( )->set_accept_callbacks
( call_opt->accept_callbacks( ) );
}
parent_->configure_message_for( clk, request, llu );
vtrc::uint64_t call_id = llu.id( );
if( llu.opt( ).wait( ) ) { /// Send and wait
context_holder ch( &llu );
ch.ctx_->set_call_options( call_opt );
ch.ctx_->set_done_closure( done );
parent_->call_and_wait( call_id, llu, controller,
response, clk, call_opt );
} else { /// Send and ... just send
parent_->call_rpc_method( clk.get( ), llu );
}
}
struct range
range_x(
struct range r1 ,
struct range r2 )
{
struct range result ;
if ( cclk(r1.c,r2.c) )
result.c = r1.c ;
else
result.c = r2.c ;
if ( clk(r1.cc,r2.cc) )
result.cc = r1.cc ;
else
result.cc = r2.cc ;
return(result) ;
}
int
sc_main (int argc, char *argv[])
{
sc_clock clk ("clk", 1, SC_US);
rng *rng1;
stimulus *st1;
rng1 = new rng ("rng");
st1 = new stimulus ("stimulus");
sc_signal < bool > reset;
sc_signal < bool > loadseed_i;
sc_signal < sc_uint < 32 > >seed_i;
sc_signal < sc_uint < 32 > >number_o;
rng1->clk (clk);
rng1->reset (reset);
rng1->loadseed_i (loadseed_i);
rng1->seed_i (seed_i);
rng1->number_o (number_o);
st1->clk (clk);
st1->reset (reset);
st1->loadseed_o (loadseed_i);
st1->seed_o (seed_i);
st1->number_i (number_o);
sc_trace_file *tf = sc_create_vcd_trace_file("rng_wave");
sc_write_comment(tf, "Random Number Generator wave trace");
tf->set_time_unit(1, SC_US);
sc_trace(tf, reset, "Reset");
sc_trace(tf, loadseed_i, "InitialSeed");
sc_trace(tf, seed_i, "Seed");
sc_trace(tf, number_o, "RandomNumber");
sc_start (1, SC_SEC);
sc_close_vcd_trace_file(tf);
return 0;
}
int sc_main(int argc, char* argv[]) {
sc_signal<sc_uint<8> > A0, A1, A2, A3;
sc_signal<sc_uint<8> > outbuf;
sc_signal<sc_uint<8> > avg;
sc_clock clk("clk", 10, SC_NS, 0.5);
reduction DUT("reduction");
DUT.clk(clk);
DUT.A0(A0);
DUT.A1(A1);
DUT.A2(A2);
DUT.A3(A3);
DUT.avg(avg);
stim STIM("stimulus");
STIM.clk(clk);
STIM.A0(A0);
STIM.A1(A1);
STIM.A2(A2);
STIM.A3(A3);
outputcollect OUTCL("outputcollect");
OUTCL.clk(clk);
OUTCL.avg(avg);
check CHECK("checker");
CHECK.clk(clk);
CHECK.avg(avg);
sc_start(SC_ZERO_TIME);
sc_trace_file *tf = sc_create_vcd_trace_file("trace");
sc_trace(tf, A0, "A0");
sc_trace(tf, A1, "A1");
sc_trace(tf, A2, "A2");
sc_trace(tf, A3, "A3");
sc_trace(tf, avg, "AVG");
sc_trace(tf, clk, "CLOCK");
sc_start(10000000, SC_NS);
sc_close_vcd_trace_file(tf);
return 0;
}
rpc_channel::lowlevel_unit_sptr make_lowlevel(
const gpb::MethodDescriptor* method,
const gpb::Message* request,
gpb::Message* response ) const
{
rpc_channel::lowlevel_unit_sptr res =
create_lowlevel( method, request, response );
common::connection_iface_sptr clk(connection_.lock( ));
if( clk.get( ) == NULL ) {
parent_->get_channel_error_callback( )( "Connection lost" );
return rpc_channel::lowlevel_unit_sptr( );
}
parent_->configure_message_for( clk, request, *res );
return res;
}
int
sc_main( int, char*[] )
{
sc_signal<int> ack;
sc_signal<int> ready;
ack = 1;
ready = 1;
sc_clock clk( "Clock", 20, SC_NS, 0.5, 0.0, SC_NS );
proc1 P1( "P1", clk, ack, ready );
proc2 P2( "P2", clk, ready, ack );
sc_start( 500, SC_NS );
return 0;
}
int sc_main(int ac, char *av[])
{
// Signal Instantiation
signal_bool_vector prime ("prime");
// Clock Instantiation
sc_clock clk ("CLK", 6, SC_NS, 0.5, 0, SC_NS); // 167 Mhz
// Process Instantiation
displayp T2 ("T2", clk, prime);
// Simulation Run Control
sc_start( 30, SC_NS, SC_EXIT_ON_STARVATION );
cout << sc_time_stamp() << " : STOPPING SIM - start button" << endl;
return 0;
}
int main(int argc, char* argv[])
{
QApplication app(argc, argv);
QWidget fenetre;
QGridLayout layt;
Clock clk(350);
//layt.addWidget(&clk,0, 0);
//fenetre.setLayout(&layt);
//clk.setParent(&fenetre);
//fenetre.setWindowFlags(Qt::FramelessWindowHint);
clk.show();
return app.exec();
}
int sc_main (int argc, char * argv[]) {
sc_clock clk ("my_clock",1,0.5);
RegisterTest *rs = new RegisterTest("RegisterTest");
rs->clock(clk.signal());
sc_trace_file *tf = sc_create_vcd_trace_file("RegisterTest");
sc_trace(tf,rs->clock,"clock");
sc_trace(tf,rs->sel,"sel");
sc_trace(tf,rs->in, "in");
sc_trace(tf,rs->out, "out");
sc_trace(tf,rs->rwBit, "rwBit");
sc_start();
sc_close_vcd_trace_file(tf);
return 0;
}
int sc_main(int ac, char **av)
{
sc_signal<bool> handshake ("HS");
sc_signal<bool> found;
sc_signal<char> stream ("ST");
sc_clock clk("Clock", 20, SC_NS, 0.5, 0.0, SC_NS);
counter cnt("COUNTER", clk, found);
fsm_recognizer fsm("Recog", clk, stream, handshake, found);
stimgen chargen("TESTB", clk, stream, handshake);
// initialize signals - ali
handshake = false;
found = false;
sc_start();
return 0;
}
byte shiftIn(int dataPin, int clockPin, BITORDER_T bitOrder) {
byte ret = 0;
CPin dat(unoPIN[dataPin]);
CPin clk(unoPIN[clockPin]);
dat.input();
clk.output(NOT_OPEN);
for (int i = 0; i < 8; ++i) {
clk = HIGH;
delayMicroseconds(2);
if ( dat==HIGH ) {
if ( bitOrder==LSBFIRST ) {
bitSet(ret, i);
} else {
bitSet(ret, (7-i));
}
}
clk = LOW;
}
return (ret);
}
int sc_main(int argc, char* argv[])
{
sc_signal<bool> din, dout;
sc_clock clk("clk",10,SC_NS,0.5); // Create a clock signal
dff DUT("dff"); // Instantiate Device Under Test
DUT.clk(clk); // Connect ports
DUT.din(din);
DUT.dout(dout);
sc_start(6, SC_NS); // Run simulation
din=true;
sc_start(14, SC_NS); // Run simulation
din=false;
sc_start(100, SC_NS); // Run simulation
return 0;
}
int sc_main(int ac, char *av[])
{
// Signal Instantiation
sc_signal_bool_vector6 in1 ("in1");
sc_signal_bool_vector6 in2 ("in2");
sc_signal_bool_vector7 result ("result");
sc_signal<bool> ready ("ready");
// Clock Instantiation
sc_clock clk( "clock", 10, SC_NS, 0.5, 0, SC_NS);
// Process Instantiation
datawidth D1 ("D1", clk, in1, in2, ready, result);
stimgen T1 ("T1", clk, result, in1, in2, ready);
// Simulation Run Control
sc_start();
return 0;
}
int sc_main(int argc, char* argv[])
{
sc_clock clk("clk", 50, SC_NS, 0.5, 0, SC_NS);
sc_signal<sc_uint<37> > a;
sc_tf = sc_create_vcd_trace_file("test13");
Mod mod("mod");
mod.clk(clk);
mod.a(a);
sc_trace(sc_tf, clk, clk.name());
sc_start(50, SC_NS);
a = 12;
sc_start(50, SC_NS);
return 0;
} // sc_main()
void nvhost_scale3d_callback(struct nvhost_device_profile *profile,
unsigned long freq)
{
struct nvhost_gr3d_params *gr3d_params = profile->private_data;
struct nvhost_device_data *pdata = platform_get_drvdata(profile->pdev);
struct nvhost_emc_params *emc_params = &gr3d_params->emc_params;
long hz;
long after;
/* Set EMC clockrate */
after = (long) clk_get_rate(clk(profile, gr3d_params->clk_3d));
hz = nvhost_scale3d_get_emc_rate(emc_params, after);
nvhost_module_set_devfreq_rate(profile->pdev, gr3d_params->clk_3d_emc,
hz);
if (pdata->gpu_edp_device) {
u32 avg = 0;
actmon_op().read_avg_norm(profile->actmon, &avg);
tegra_edp_notify_gpu_load(avg);
}
}
double run(const int num_trials) {
fprintf(stderr,"run\n");
fprintf(stderr,"size = %d\n",size);
fprintf(stderr,"num_trials = %d\n",num_trials);
fprintf(stderr,"data = %p\n",data);
assert(status==2);
TimeStat clk(num_trials);
double *tmp=(double*)malloc(sizeof(double)*size*2);
assert(tmp);
for (int i = 0; i < num_trials; i++) {
//printf("\t%d\n",i);
memcpy(tmp,data,sizeof(double)*size*2);
double _Complex pos[2];
clk.tic();
closest_pair(size,tmp,pos);
clk.toc();
}
free(tmp);
status=3;
return clk.median();
}
void testDataPath(){
bus clk ("P"); // Clock pulse
bus rst ("0");
bus a_bus("1010"); // 10
bus b_bus("0011"); // 3
bus en_quoCount("1");
bus r_bus, q_bus;
bus greater, equal, lesser;
DividerDatapath * DP = new DividerDatapath(clk, rst,
a_bus, b_bus,
r_bus, q_bus,
en_quoCount, greater, equal, lesser);
DP->eval();
DP->printValues();
DP->eval();
DP->printValues();
}
int sc_main(int ac, char *av[])
{
// Signal Instantiation
sc_signal<bool> reset ("reset");
sc_signal<bool> prime_ready ("prime_ready");
signal_bool_vector prime ("prime");
// Clock Instantiation
sc_clock clk ("CLK", 6, SC_NS, 0.5, 10, SC_NS, false); // 167 Mhz
// Process Instantiation
prime_numgen D1 ("D1", clk, reset, prime_ready, prime);
resetp T1 ("T1", clk, reset);
displayp T2 ("T2", clk, prime_ready, prime);
// Simulation Run Control
sc_start();
return 0;
}
int sc_main(int ac, char *av[])
{
sc_signal<double> in1;
sc_signal<double> in2;
sc_signal<double> sum;
sc_signal<double> diff;
sc_signal<double> prod;
sc_signal<double> quot;
sc_signal<double> powr;
powr = 0.0;
sc_clock clk("CLOCK", 20.0, SC_NS, 0.5, 0.0, SC_NS);
numgen N("STIMULUS", clk, in1, in2);
stage1 S1("Stage1", clk, in1, in2, sum, diff);
stage2 S2("Stage2", clk, sum, diff, prod, quot);
stage3 S3("Stage3", clk, prod, quot, powr);
display D("Display", clk, powr);
sc_start(1000, SC_NS);
return 0;
}
int
sc_main( int argc, char* argv[] )
{
sc_signal<int> a("a");
sc_signal<int> b("b");
sc_signal<int> c("c");
sc_clock clk("clk", 10, SC_NS);
example ex1("ex1");
ex1(clk, a, b, c);
tb tbb1("tbb1");
tbb1(clk, a);
tb2 tbb2("tbb2");
tbb2(clk, b);
monitor mon("mon", a, b, c);
sc_start(200, SC_NS);
return 0;
}
int sc_main( int argc, char *argv[] ) {
// Signals
sc_signal<int> arg1;
sc_signal<int> arg2;
sc_signal<int> sum;
// Clock
sc_clock clk( "clock", 10, 0.5 );
// Module
stimuli *S;
adder *A;
display *D;
// Module instantiations and Mapping
S = new stimuli("stimuli");
//(*S) (arg1, arg2, clk);
A = new adder("adder");
//(*A) (arg1, arg2, sum);
D = new display ("display");
//(*D) (sum);
S->clk(clk);
S->out1(arg1);
S->out2(arg2);
A->clk(clk);
A->in1(arg1);
A->in2(arg2);
A->out1(sum);
D->clk(clk);
D->in1(sum);
// Start of the Simulation
sc_start(200);
return 0;
};
int sc_main(int argc, char *argv[])
{
sc_signal<int> s1, s2;
sc_clock clk("c1", 1, SC_NS);
top top1("Top1");
top1.clk(clk);
top1.input(s1);
top1.output(s2);
stimulus sti1("stimulus1");
sti1.clk(clk);
sti1.x(s1);
monitor mon1("monitor1");
mon1.clk(clk);
mon1.z(s2);
sc_start(20, SC_NS);
return 0;
}
int sc_main(int argc, char* argv[]) {
sc_signal<bool> enable, rw, clr;
sc_clock clk("clk",10,SC_NS);
sc_signal<sc_uint<32> > din, dout;
sc_trace_file *fp; // VCD filepointer
fp=sc_create_vcd_trace_file("wave");// Create wave.vcd file
sc_trace(fp,clk,"clk"); // Add signals to trace file
sc_trace(fp,enable,"enable");
sc_trace(fp,rw,"rw");
sc_trace(fp,clr,"clr");
sc_trace(fp,din,"din");
sc_trace(fp,dout,"dout");
//register
reg REG("reg");
REG.clk(clk);
REG.enable(enable);
REG.rw(rw);
REG.clr(clr);
REG.din(din);
REG.dout(dout);
//stim
stim STIM("stim");
STIM.clk(clk);
STIM.enable(enable);
STIM.rw(rw);
STIM.clr(clr);
STIM.din(din);
sc_start(1000, SC_NS); //start simulation
sc_close_vcd_trace_file(fp); // close wave.vcd
return 0; // Return OK, no errors.
}