/**
* @brief Perform basic hardware initialization
*
* Initialize the interrupt controller device drivers.
* Also initialize the timer device driver, if required.
*
* @return 0
*/
static int silabs_efm32wg_init(struct device *arg)
{
ARG_UNUSED(arg);
int oldLevel; /* old interrupt lock level */
/* disable interrupts */
oldLevel = irq_lock();
/* handle chip errata */
CHIP_Init();
_ClearFaults();
/* Initialize system clock according to CONFIG_CMU settings */
clkInit();
/*
* install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
/* restore interrupt state */
irq_unlock(oldLevel);
return 0;
}
void Startup::init()
{
register unsigned long *pulSrc, *pulDest;
// Init system clock
clkInit();
// Copy the data segment initializers from flash to SRAM.
pulSrc = &_flash_data;
for(pulDest = &_data; pulDest < &_edata; )
{
*(pulDest++) = *(pulSrc++);
}
// Zero fill the bss segment.
for(pulDest = &_bss; pulDest < &_ebss; )
{
*(pulDest++) = 0;
}
/* // Fill the stack with a known value.
for(pulDest = pulStack; pulDest < pulStack + STACK_SIZE; )
{
*pulDest++ = 0xA5A5;
}
*/
// Call global/static constructors (used with arm-none-eabi toolchain)
init_array();
//
__do_global_ctors();
}
void DeviceLM74::init(void)
{
OSDeviceDebug::putString_P(PSTR("DeviceLM74::init()"));
OSDeviceDebug::putNewLine();
implSelectInit();
clkInit();
dataIn();
}
int main(void)
{
float old_frequency = 0.0, old_amplitude = 0.0, old_power = 0.40;
clkInit();
gpioInit();
// motor PWM module initialization
PWM_Init();
// software PWM for RGB initializaiton
RGB_init(); // place it after sindrive init so it doesn't slow down initial calculation
RGB_set(RGB_RED);
// motor driver IC initialization
init_DRV8301();
spiSlave_Init();
spiMaster_Init_Cry();
// BLDC motor control initialization
SineDrive_init();
SineDrive_setMotorMovement(old_frequency, old_amplitude, old_power, 3000);
SineDrive_do();
for (;;)
{
if (Update) {
Update = 0;
set_led_color_from_state();
if((old_frequency != get_frequency_from_state()) || (old_amplitude != get_amplitude_from_state()))
{
old_frequency = get_frequency_from_state();
old_amplitude = get_amplitude_from_state();
SineDrive_setMotorMovement(old_frequency, old_amplitude, old_power, 3000);
// SineDrive_setMotorMovement(2.0, 0.4, 0.40, 3000);
}
SineDrive_do();
}
}
}
void main(void) {
WDTCTL = WDTPW + WDTHOLD;
_disable_interrupts();
clkInit(DCO_FREQ);
CHG_CONFIG();
//LED_RED_CONFIG();
//LED_GREEN_CONFIG();
//SW1_CONFIG();
_enable_interrupts();
#ifdef CDC_CONT
//register ADC with default codeword for continuous sampling
myCDC = registerCDC(CDC_CHEN1 | CDC_CHEN2 | CDC_SAMPLEC);
// resetCDC();
__delay_cycles(250000);
setCDC(myCDC);
writeRegCDC(CDC_POS, CDC_DACPEN | 0x01); //setup the CAPDAC (vertical offset capacitance compensation)
writeRegCDC(CDC_SETUP1, CDC_SE_25pF); //set the full scale range
startCDC();
while (1) {
_nop();
// writeRegCDC(testReg, testVal);
_nop();
readRegCDC(CDC_STATUS, 16);
}
#else
myADC = registerADS(ADS_01, ADS_DEFAULT1); //register ADc with default codeword for 1 shot sampling
setADS(myADC);
while(1) {
a = singleShotADS();
}
#endif
}
static int fsl_frdm_k64f_init(struct device *arg)
{
ARG_UNUSED(arg);
int oldLevel; /* old interrupt lock level */
#if !defined(CONFIG_HAS_SYSMPU)
u32_t temp_reg;
#endif /* !CONFIG_HAS_SYSMPU */
/* disable interrupts */
oldLevel = irq_lock();
/* release I/O power hold to allow normal run state */
PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
#if !defined(CONFIG_HAS_SYSMPU)
/*
* Disable memory protection and clear slave port errors.
* Note that the K64F does not implement the optional ARMv7-M memory
* protection unit (MPU), specified by the architecture (PMSAv7), in the
* Cortex-M4 core. Instead, the processor includes its own MPU module.
*/
temp_reg = SYSMPU->CESR;
temp_reg &= ~SYSMPU_CESR_VLD_MASK;
temp_reg |= SYSMPU_CESR_SPERR_MASK;
SYSMPU->CESR = temp_reg;
#endif /* !CONFIG_HAS_SYSMPU */
_ClearFaults();
/* Initialize PLL/system clock to 120 MHz */
clkInit();
/*
* install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
/* restore interrupt state */
irq_unlock(oldLevel);
return 0;
}
void main(void) {
WDTCTL = WDTPW + WDTHOLD;
_disable_interrupts();
clkInit(DCO_FREQ);
CHG_CONFIG();
//LED_RED_CONFIG();
//LED_GREEN_CONFIG();
//SW1_CONFIG();
_enable_interrupts();
#ifdef TMP_CONT
//register ADC with default codeword for continuous sampling
myTMP = registerTMP(TMP100_01, TMP_DEFAULTC);
setTMP(myTMP);
startTMP();
writeLongTMP(TMP_HI_THRESH, TMP_REF_100);//demo write register
while (1) {
a = readLongTMP(TMP_LO_THRESH);
_nop();
a = readLongTMP(TMP_HI_THRESH);
_nop();
a = readConfigTMP();
_nop();
a = readLongTMP(TMP_TEMP);
_nop();
}
#else
myTMP = registerTMP(TMP100_01, TMP_DEFAULT1); //register ADc with default codeword for 1 shot sampling
setTMP(myTMP);
while(1){
a = singleShotTMP();
}
#endif
}
static ALWAYS_INLINE void clkInit(void)
{
/*
* Core clock: 48MHz
* Bus clock: 24MHz
*/
const mcg_pll_config_t pll0Config = {
.enableMode = 0U, .prdiv = CONFIG_MCG_PRDIV0, .vdiv = CONFIG_MCG_VDIV0,
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.er32kSrc = 3U, /* ERCLK32K selection, use LPO. */
.clkdiv1 = 0x10010000U, /* SIM_CLKDIV1. */
};
const osc_config_t oscConfig = {.freq = CONFIG_OSC_XTAL0_FREQ,
.capLoad = 0,
#if defined(CONFIG_OSC_EXTERNAL)
.workMode = kOSC_ModeExt,
#elif defined(CONFIG_OSC_LOW_POWER)
.workMode = kOSC_ModeOscLowPower,
#elif defined(CONFIG_OSC_HIGH_GAIN)
.workMode = kOSC_ModeOscHighGain,
#else
#error "An oscillator mode must be defined"
#endif
.oscerConfig = {
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && \
FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
} };
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
#ifdef CONFIG_UART_MCUX_LPSCI_0
CLOCK_SetLpsci0Clock(LPSCI0SRC_MCGFLLCLK);
#endif
}
static int kl2x_init(struct device *arg)
{
ARG_UNUSED(arg);
int oldLevel; /* old interrupt lock level */
/* disable interrupts */
oldLevel = irq_lock();
/* Disable the watchdog */
SIM->COPC = 0;
/* Initialize system clock to 48 MHz */
clkInit();
/*
* install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
/* restore interrupt state */
irq_unlock(oldLevel);
return 0;
}
SYS_INIT(kl2x_init, PRE_KERNEL_1, 0);
static int fsl_frdm_k64f_init(struct device *arg)
{
ARG_UNUSED(arg);
/* System Integration module */
volatile struct K20_SIM *sim_p =
(volatile struct K20_SIM *)PERIPH_ADDR_BASE_SIM;
/* Power Mgt Control module */
volatile struct K6x_PMC *pmc_p =
(volatile struct K6x_PMC *)PERIPH_ADDR_BASE_PMC;
/* Power Mgt Control module */
volatile struct K6x_MPU *mpu_p =
(volatile struct K6x_MPU *)PERIPH_ADDR_BASE_MPU;
int oldLevel; /* old interrupt lock level */
uint32_t temp_reg;
/* disable interrupts */
oldLevel = irq_lock();
/* enable the port clocks */
sim_p->scgc5.value |= (SIM_SCGC5_PORTA_CLK_EN | SIM_SCGC5_PORTB_CLK_EN |
SIM_SCGC5_PORTC_CLK_EN | SIM_SCGC5_PORTD_CLK_EN |
SIM_SCGC5_PORTE_CLK_EN);
/* release I/O power hold to allow normal run state */
pmc_p->regsc.value |= PMC_REGSC_ACKISO_MASK;
/*
* Disable memory protection and clear slave port errors.
* Note that the K64F does not implement the optional ARMv7-M memory
* protection unit (MPU), specified by the architecture (PMSAv7), in the
* Cortex-M4 core. Instead, the processor includes its own MPU module.
*/
temp_reg = mpu_p->ctrlErrStatus.value;
temp_reg &= ~MPU_VALID_MASK;
temp_reg |= MPU_SLV_PORT_ERR_MASK;
mpu_p->ctrlErrStatus.value = temp_reg;
/* clear all faults */
_ScbMemFaultAllFaultsReset();
_ScbBusFaultAllFaultsReset();
_ScbUsageFaultAllFaultsReset();
_ScbHardFaultAllFaultsReset();
/*
* Initialize the clock dividers for:
* core and system clocks = 120 MHz (PLL/OUTDIV1)
* bus clock = 60 MHz (PLL/OUTDIV2)
* FlexBus clock = 40 MHz (PLL/OUTDIV3)
* Flash clock = 24 MHz (PLL/OUTDIV4)
*/
sim_p->clkdiv1.value = (
(SIM_CLKDIV(CONFIG_K64_CORE_CLOCK_DIVIDER) <<
SIM_CLKDIV1_OUTDIV1_SHIFT) |
(SIM_CLKDIV(CONFIG_K64_BUS_CLOCK_DIVIDER) <<
SIM_CLKDIV1_OUTDIV2_SHIFT) |
(SIM_CLKDIV(CONFIG_K64_FLEXBUS_CLOCK_DIVIDER) <<
SIM_CLKDIV1_OUTDIV3_SHIFT) |
(SIM_CLKDIV(CONFIG_K64_FLASH_CLOCK_DIVIDER) <<
SIM_CLKDIV1_OUTDIV4_SHIFT));
/* Initialize PLL/system clock to 120 MHz */
clkInit();
/*
* install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
/* restore interrupt state */
irq_unlock(oldLevel);
return 0;
}
