static int clk_pllv3_power_up_down(struct clk_hw *hw, bool enable)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
u32 val, ret = 0;
if (enable) {
val = readl_relaxed(pll->base);
val &= ~BM_PLL_BYPASS;
if (pll->powerup_set)
val |= BM_PLL_POWER;
else
val &= ~BM_PLL_POWER;
writel_relaxed(val, pll->base);
ret = clk_pllv3_wait_lock(pll);
} else {
val = readl_relaxed(pll->base);
val |= BM_PLL_BYPASS;
if (pll->powerup_set)
val &= ~BM_PLL_POWER;
else
val |= BM_PLL_POWER;
writel_relaxed(val, pll->base);
}
if (!ret) {
val = readl_relaxed(pll->base);
val &= ~BM_PLL_BYPASS;
writel_relaxed(val, pll->base);
}
return ret;
}
static int clk_pllv3_do_hardware(struct clk_hw *hw, bool enable)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
u32 val;
int ret;
val = readl_relaxed(pll->base);
if (enable) {
if (pll->powerup_set)
val |= BM_PLL_POWER;
else
val &= ~BM_PLL_POWER;
writel_relaxed(val, pll->base);
ret = clk_pllv3_wait_lock(pll);
if (ret)
return ret;
} else {
if (pll->powerup_set)
val &= ~BM_PLL_POWER;
else
val |= BM_PLL_POWER;
writel_relaxed(val, pll->base);
}
return 0;
}
static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
unsigned long min_rate = parent_rate * 27;
unsigned long max_rate = parent_rate * 54;
u32 val, div;
u32 mfn, mfd = 1000000;
s64 temp64;
if (rate < min_rate || rate > max_rate)
return -EINVAL;
div = rate / parent_rate;
temp64 = (u64) (rate - div * parent_rate);
temp64 *= mfd;
do_div(temp64, parent_rate);
mfn = temp64;
val = readl_relaxed(pll->base);
val &= ~pll->div_mask;
val |= div;
writel_relaxed(val, pll->base);
writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
return clk_pllv3_wait_lock(pll);
}
static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
unsigned long min_rate = parent_rate * 54 / 2;
unsigned long max_rate = parent_rate * 108 / 2;
u32 val, div;
if (rate < min_rate || rate > max_rate)
return -EINVAL;
div = rate * 2 / parent_rate;
val = readl_relaxed(pll->base);
val &= ~pll->div_mask;
val |= div;
writel_relaxed(val, pll->base);
return clk_pllv3_wait_lock(pll);
}
static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
u32 val, div;
if (rate == parent_rate * 22)
div = 1;
else if (rate == parent_rate * 20)
div = 0;
else
return -EINVAL;
val = readl_relaxed(pll->base);
val &= ~pll->div_mask;
val |= div;
writel_relaxed(val, pll->base);
return clk_pllv3_wait_lock(pll);
}
static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
unsigned long min_rate = parent_rate * 54 / 2;
unsigned long max_rate = parent_rate * 108 / 2;
u32 val, div;
if (rate != BYPASS_RATE && (rate < min_rate || rate > max_rate))
return -EINVAL;
pll->rate_req = rate;
val = readl_relaxed(pll->base);
if (rate == BYPASS_RATE) {
/*
* Set the PLL in bypass mode if rate requested is
* BYPASS_RATE.
*/
val |= BM_PLL_BYPASS;
/* Power down the PLL. */
if (pll->powerup_set)
val &= ~BM_PLL_POWER;
else
val |= BM_PLL_POWER;
writel_relaxed(val, pll->base);
return 0;
}
div = rate * 2 / parent_rate;
val = readl_relaxed(pll->base);
val &= ~pll->div_mask;
val |= div;
writel_relaxed(val, pll->base);
return clk_pllv3_wait_lock(pll);
}
static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
u32 val, div;
pll->rate_req = rate;
val = readl_relaxed(pll->base);
/* If the PLL is bypassed, its rate is 24MHz. */
if (rate == BYPASS_RATE) {
/* Set the bypass bit. */
val |= BM_PLL_BYPASS;
/* Power down the PLL. */
if (pll->powerup_set)
val &= ~BM_PLL_POWER;
else
val |= BM_PLL_POWER;
writel_relaxed(val, pll->base);
return 0;
}
if (rate == parent_rate * 22)
div = 1;
else if (rate == parent_rate * 20)
div = 0;
else
return -EINVAL;
val = readl_relaxed(pll->base);
val &= ~pll->div_mask;
val |= div;
writel_relaxed(val, pll->base);
return clk_pllv3_wait_lock(pll);
}
static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
unsigned long min_rate = parent_rate * 27;
unsigned long max_rate = parent_rate * 54;
u32 val, newval, div;
u32 mfn, mfd = 1000000;
s64 temp64;
int ret;
if (rate != BYPASS_RATE && (rate < min_rate || rate > max_rate))
return -EINVAL;
pll->rate_req = rate;
val = readl_relaxed(pll->base);
if (rate == BYPASS_RATE) {
/*
* Set the PLL in bypass mode if rate requested is
* BYPASS_RATE.
*/
/* Bypass the PLL */
val |= BM_PLL_BYPASS;
/* Power down the PLL. */
if (pll->powerup_set)
val &= ~BM_PLL_POWER;
else
val |= BM_PLL_POWER;
writel_relaxed(val, pll->base);
return 0;
}
/* Else clear the bypass bit. */
val &= ~BM_PLL_BYPASS;
writel_relaxed(val, pll->base);
div = rate / parent_rate;
temp64 = (u64) (rate - div * parent_rate);
temp64 *= mfd;
do_div(temp64, parent_rate);
mfn = temp64;
val = readl_relaxed(pll->base);
/* set the PLL into bypass mode */
newval = val | BM_PLL_BYPASS;
writel_relaxed(newval, pll->base);
/* configure the new frequency */
newval &= ~pll->div_mask;
newval |= div;
writel_relaxed(newval, pll->base);
writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
writel(mfd, pll->base + PLL_DENOM_OFFSET);
ret = clk_pllv3_wait_lock(pll);
if (ret == 0 && val & BM_PLL_POWER) {
/* only if it locked can we switch back to the PLL */
newval &= ~BM_PLL_BYPASS;
newval |= val & BM_PLL_BYPASS;
writel(newval, pll->base);
}
return ret;
}
