static int
jz4780_mmc_enable_clock(struct jz4780_mmc_softc *sc)
{
int err;
err = clk_get_by_ofw_name(sc->sc_dev, 0, "mmc", &sc->sc_clk);
if (err == 0)
err = clk_enable(sc->sc_clk);
if (err == 0)
err = clk_set_freq(sc->sc_clk, sc->sc_host.f_max, 0);
if (err != 0)
clk_release(sc->sc_clk);
return (err);
}
static void
process_msg(struct tegra_xhci_softc *sc, uint32_t req_cmd, uint32_t req_data,
uint32_t *resp_cmd, uint32_t *resp_data)
{
uint64_t freq;
int rv;
/* In most cases, data are echoed back. */
*resp_data = req_data;
switch (req_cmd) {
case MBOX_CMD_INC_FALC_CLOCK:
case MBOX_CMD_DEC_FALC_CLOCK:
rv = clk_set_freq(sc->clk_xusb_falcon_src, req_data * 1000ULL,
0);
if (rv == 0) {
rv = clk_get_freq(sc->clk_xusb_falcon_src, &freq);
*resp_data = (uint32_t)(freq / 1000);
}
*resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK;
break;
case MBOX_CMD_INC_SSPI_CLOCK:
case MBOX_CMD_DEC_SSPI_CLOCK:
rv = clk_set_freq(sc->clk_xusb_ss, req_data * 1000ULL,
0);
if (rv == 0) {
rv = clk_get_freq(sc->clk_xusb_ss, &freq);
*resp_data = (uint32_t)(freq / 1000);
}
*resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK;
break;
case MBOX_CMD_SET_BW:
/* No respense is expected. */
*resp_cmd = 0;
break;
case MBOX_CMD_SET_SS_PWR_GATING:
case MBOX_CMD_SET_SS_PWR_UNGATING:
*resp_cmd = MBOX_CMD_NAK;
break;
case MBOX_CMD_SAVE_DFE_CTLE_CTX:
/* Not implemented yet. */
*resp_cmd = MBOX_CMD_ACK;
break;
case MBOX_CMD_START_HSIC_IDLE:
case MBOX_CMD_STOP_HSIC_IDLE:
/* Not implemented yet. */
*resp_cmd = MBOX_CMD_NAK;
break;
case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
/* Not implemented yet. */
*resp_cmd = MBOX_CMD_NAK;
break;
case MBOX_CMD_AIRPLANE_MODE_ENABLED:
case MBOX_CMD_AIRPLANE_MODE_DISABLED:
case MBOX_CMD_DBC_WAKE_STACK:
case MBOX_CMD_HSIC_PRETEND_CONNECT:
case MBOX_CMD_RESET_SSPI:
device_printf(sc->dev,
"Received unused/unexpected command: %u\n", req_cmd);
*resp_cmd = 0;
break;
default:
device_printf(sc->dev,
"Received unknown command: %u\n", req_cmd);
}
}
static int
enable_fdt_resources(struct tegra_xhci_softc *sc)
{
int rv;
rv = hwreset_assert(sc->hwreset_xusb_host);
if (rv != 0) {
device_printf(sc->dev, "Cannot reset 'xusb_host' reset\n");
return (rv);
}
rv = hwreset_assert(sc->hwreset_xusb_ss);
if (rv != 0) {
device_printf(sc->dev, "Cannot reset 'xusb_ss' reset\n");
return (rv);
}
rv = regulator_enable(sc->supply_avddio_pex);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avddio_pex' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_dvddio_pex);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'dvddio_pex' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_usb);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_usb' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_pll_utmip);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_pll_utmip-5v' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_pll_erefe);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_pll_erefe' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_usb_ss_pll);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_usb_ss_pll' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_hvdd_usb_ss);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'hvdd_usb_ss' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_hvdd_usb_ss_pll_e);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'hvdd_usb_ss_pll_e' regulator\n");
return (rv);
}
/* Power off XUSB host and XUSB SS domains. */
rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerdown 'xusba' domain\n");
return (rv);
}
rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerdown 'xusbc' domain\n");
return (rv);
}
/* Setup XUSB ss_src clock first */
clk_set_freq(sc->clk_xusb_ss, TEGRA_XHCI_SS_HIGH_SPEED, 0);
if (rv != 0)
return (rv);
/* The XUSB gate clock must be enabled before XUSBA can be powered. */
rv = clk_enable(sc->clk_xusb_gate);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_gate' clock\n");
return (rv);
}
/* Power on XUSB host and XUSB SS domains. */
rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
sc->clk_xusb_host, sc->hwreset_xusb_host);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerup 'xusbc' domain\n");
return (rv);
}
rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
sc->clk_xusb_ss, sc->hwreset_xusb_ss);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerup 'xusba' domain\n");
return (rv);
}
/* Enable rest of clocks */
rv = clk_enable(sc->clk_xusb_falcon_src);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_falcon_src' clock\n");
return (rv);
}
rv = clk_enable(sc->clk_xusb_fs_src);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_fs_src' clock\n");
return (rv);
}
rv = clk_enable(sc->clk_xusb_hs_src);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_hs_src' clock\n");
return (rv);
}
rv = phy_enable(sc->phy_usb2_0);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB2_0 phy\n");
return (rv);
}
rv = phy_enable(sc->phy_usb2_1);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB2_1 phy\n");
return (rv);
}
rv = phy_enable(sc->phy_usb2_2);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB2_2 phy\n");
return (rv);
}
rv = phy_enable(sc->phy_usb3_0);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB3_0 phy\n");
return (rv);
}
return (0);
}
struct eth_driver*
ethif_plat_init(int dev_id, struct ethif_os_interface interface) {
struct enet * enet;
struct ocotp * ocotp;
struct clock* arm_clk;
struct imx6_eth_data *eth_data;
struct ldesc* ldesc;
(void)dev_id;
os_iface_init(interface);
eth_data = (struct imx6_eth_data*)os_malloc(sizeof(struct imx6_eth_data));
if (eth_data == NULL) {
cprintf(COL_IMP, "Failed to allocate dma buffers\n");
return NULL;
}
ldesc = ldesc_init(RX_DESC_COUNT, RXBUF_SIZE, TX_DESC_COUNT, TXBUF_SIZE);
assert(ldesc);
/*
* We scale up the CPU to improve benchmarking performance
* It is not the right place so should be moved later
*/
arm_clk = clk_get_clock(CLK_ARM);
clk_set_freq(arm_clk, CPU_FREQ);
CLK_DEBUG(printf("ARM clock frequency: %9d HZ\n", clk_get_freq(arm_clk)));
/* initialise the eFuse controller so we can get a MAC address */
ocotp = ocotp_init();
/* Initialise ethernet pins */
gpio_init();
setup_iomux_enet();
/* Initialise the phy library */
miiphy_init();
/* Initialise the phy */
phy_micrel_init();
/* Initialise the RGMII interface */
enet = enet_init(ldesc);
assert(enet);
/* Fetch and set the MAC address */
if(ocotp == NULL || ocotp_get_mac(ocotp, eth_data->ethaddr)){
memcpy(eth_data->ethaddr, DEFAULT_MAC, 6);
}
enet_set_mac(enet, eth_data->ethaddr);
/* Connect the phy to the ethernet controller */
if(fec_init(CONFIG_FEC_MXC_PHYMASK, enet)){
return NULL;
}
/* Start the controller */
enet_enable(enet);
/* Update book keeping */
eth_data->irq_enabled = 0;
eth_data->enet = enet;
eth_data->ldesc = ldesc;
eth_driver_set_data(&imx6_eth_driver, eth_data);
/* done */
return &imx6_eth_driver;
}
static int
jzlcd_set_videomode(struct jzlcd_softc *sc, const struct videomode *mode)
{
u_int hbp, hfp, hsw, vbp, vfp, vsw;
u_int hds, hde, ht, vds, vde, vt;
uint32_t ctrl;
int error;
hbp = mode->htotal - mode->hsync_end;
hfp = mode->hsync_start - mode->hdisplay;
hsw = mode->hsync_end - mode->hsync_start;
vbp = mode->vtotal - mode->vsync_end;
vfp = mode->vsync_start - mode->vdisplay;
vsw = mode->vsync_end - mode->vsync_start;
hds = hsw + hbp;
hde = hds + mode->hdisplay;
ht = hde + hfp;
vds = vsw + vbp;
vde = vds + mode->vdisplay;
vt = vde + vfp;
/* Setup timings */
LCD_WRITE(sc, LCDVAT,
(ht << LCDVAT_HT_SHIFT) | (vt << LCDVAT_VT_SHIFT));
LCD_WRITE(sc, LCDDAH,
(hds << LCDDAH_HDS_SHIFT) | (hde << LCDDAH_HDE_SHIFT));
LCD_WRITE(sc, LCDDAV,
(vds << LCDDAV_VDS_SHIFT) | (vde << LCDDAV_VDE_SHIFT));
LCD_WRITE(sc, LCDHSYNC, hsw);
LCD_WRITE(sc, LCDVSYNC, vsw);
/* Set configuration */
LCD_WRITE(sc, LCDCFG, LCDCFG_NEWDES | LCDCFG_RECOVER | LCDCFG_24 |
LCDCFG_PSM | LCDCFG_CLSM | LCDCFG_SPLM | LCDCFG_REVM | LCDCFG_PCP);
ctrl = LCD_READ(sc, LCDCTRL);
ctrl &= ~LCDCTRL_BST;
ctrl |= LCDCTRL_BST_64 | LCDCTRL_OFUM;
LCD_WRITE(sc, LCDCTRL, ctrl);
LCD_WRITE(sc, LCDPCFG, PCFG_MAGIC);
LCD_WRITE(sc, LCDRGBC, LCDRGBC_RGBFMT);
/* Update registers */
LCD_WRITE(sc, LCDSTATE, 0);
/* Setup frame descriptors */
jzlcd_setup_descriptor(sc, mode, 0);
jzlcd_setup_descriptor(sc, mode, 1);
bus_dmamap_sync(sc->fdesc_tag, sc->fdesc_map, BUS_DMASYNC_PREWRITE);
/* Setup DMA channels */
LCD_WRITE(sc, LCDDA0, sc->fdesc_paddr
+ sizeof(struct lcd_frame_descriptor));
LCD_WRITE(sc, LCDDA1, sc->fdesc_paddr);
/* Set display clock */
error = clk_set_freq(sc->clk_pix, DOT_CLOCK_TO_HZ(mode->dot_clock), 0);
if (error != 0) {
device_printf(sc->dev, "failed to set pixel clock to %u Hz\n",
DOT_CLOCK_TO_HZ(mode->dot_clock));
return (error);
}
return (0);
}
static int
aw_ir_attach(device_t dev)
{
struct aw_ir_softc *sc;
hwreset_t rst_apb;
clk_t clk_ir, clk_gate;
int err;
uint32_t val = 0;
clk_ir = clk_gate = NULL;
rst_apb = NULL;
sc = device_get_softc(dev);
sc->dev = dev;
if (bus_alloc_resources(dev, aw_ir_spec, sc->res) != 0) {
device_printf(dev, "could not allocate memory resource\n");
return (ENXIO);
}
switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
case A10_IR:
sc->fifo_size = 16;
break;
case A13_IR:
sc->fifo_size = 64;
break;
}
/* De-assert reset */
if (hwreset_get_by_ofw_name(dev, 0, "apb", &rst_apb) == 0) {
err = hwreset_deassert(rst_apb);
if (err != 0) {
device_printf(dev, "cannot de-assert reset\n");
goto error;
}
}
/* Reset buffer */
aw_ir_buf_reset(sc);
/* Get clocks and enable them */
err = clk_get_by_ofw_name(dev, 0, "apb", &clk_gate);
if (err != 0) {
device_printf(dev, "Cannot get gate clock\n");
goto error;
}
err = clk_get_by_ofw_name(dev, 0, "ir", &clk_ir);
if (err != 0) {
device_printf(dev, "Cannot get IR clock\n");
goto error;
}
/* Set clock rate */
err = clk_set_freq(clk_ir, AW_IR_BASE_CLK, 0);
if (err != 0) {
device_printf(dev, "cannot set IR clock rate\n");
goto error;
}
/* Enable clocks */
err = clk_enable(clk_gate);
if (err != 0) {
device_printf(dev, "Cannot enable clk gate\n");
goto error;
}
err = clk_enable(clk_ir);
if (err != 0) {
device_printf(dev, "Cannot enable IR clock\n");
goto error;
}
if (bus_setup_intr(dev, sc->res[1],
INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_ir_intr, sc,
&sc->intrhand)) {
bus_release_resources(dev, aw_ir_spec, sc->res);
device_printf(dev, "cannot setup interrupt handler\n");
return (ENXIO);
}
/* Enable CIR Mode */
WRITE(sc, AW_IR_CTL, AW_IR_CTL_MD);
/*
* Set clock sample, filter, idle thresholds.
* Frequency sample = 3MHz/128 = 23437.5Hz (42.7us)
*/
val = AW_IR_SAMPLE_128;
val |= (AW_IR_RXFILT_VAL | AW_IR_RXIDLE_VAL);
val |= (AW_IR_ACTIVE_T | AW_IR_ACTIVE_T_C);
WRITE(sc, AW_IR_CIR, val);
/* Invert Input Signal */
WRITE(sc, AW_IR_RXCTL, AW_IR_RXCTL_RPPI);
/* Clear All RX Interrupt Status */
WRITE(sc, AW_IR_RXSTA, AW_IR_RXSTA_CLEARALL);
/*
* Enable RX interrupt in case of overflow, packet end
* and FIFO available.
* RX FIFO Threshold = FIFO size / 2
*/
WRITE(sc, AW_IR_RXINT, AW_IR_RXINT_ROI_EN | AW_IR_RXINT_RPEI_EN |
AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RAL((sc->fifo_size >> 1) - 1));
/* Enable IR Module */
val = READ(sc, AW_IR_CTL);
WRITE(sc, AW_IR_CTL, val | AW_IR_CTL_GEN | AW_IR_CTL_RXEN);
sc->sc_evdev = evdev_alloc();
evdev_set_name(sc->sc_evdev, device_get_desc(sc->dev));
evdev_set_phys(sc->sc_evdev, device_get_nameunit(sc->dev));
evdev_set_id(sc->sc_evdev, BUS_HOST, 0, 0, 0);
evdev_support_event(sc->sc_evdev, EV_SYN);
evdev_support_event(sc->sc_evdev, EV_MSC);
evdev_support_msc(sc->sc_evdev, MSC_SCAN);
err = evdev_register(sc->sc_evdev);
if (err) {
device_printf(dev,
"failed to register evdev: error=%d\n", err);
goto error;
}
return (0);
error:
if (clk_gate != NULL)
clk_release(clk_gate);
if (clk_ir != NULL)
clk_release(clk_ir);
if (rst_apb != NULL)
hwreset_release(rst_apb);
evdev_free(sc->sc_evdev);
sc->sc_evdev = NULL; /* Avoid double free */
bus_release_resources(dev, aw_ir_spec, sc->res);
return (ENXIO);
}
static int
tegra_i2c_attach(device_t dev)
{
int rv, rid;
phandle_t node;
struct tegra_i2c_softc *sc;
uint64_t freq;
sc = device_get_softc(dev);
sc->dev = dev;
node = ofw_bus_get_node(dev);
LOCK_INIT(sc);
/* Get the memory resource for the register mapping. */
rid = 0;
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (sc->mem_res == NULL) {
device_printf(dev, "Cannot map registers.\n");
rv = ENXIO;
goto fail;
}
/* Allocate our IRQ resource. */
rid = 0;
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_ACTIVE);
if (sc->irq_res == NULL) {
device_printf(dev, "Cannot allocate interrupt.\n");
rv = ENXIO;
goto fail;
}
/* FDT resources. */
rv = clk_get_by_ofw_name(dev, 0, "div-clk", &sc->clk);
if (rv != 0) {
device_printf(dev, "Cannot get i2c clock: %d\n", rv);
goto fail;
}
rv = hwreset_get_by_ofw_name(sc->dev, 0, "i2c", &sc->reset);
if (rv != 0) {
device_printf(sc->dev, "Cannot get i2c reset\n");
return (ENXIO);
}
rv = OF_getencprop(node, "clock-frequency", &sc->bus_freq,
sizeof(sc->bus_freq));
if (rv != sizeof(sc->bus_freq)) {
sc->bus_freq = 100000;
goto fail;
}
/* Request maximum frequency for I2C block 136MHz (408MHz / 3). */
rv = clk_set_freq(sc->clk, 136000000, CLK_SET_ROUND_DOWN);
if (rv != 0) {
device_printf(dev, "Cannot set clock frequency\n");
goto fail;
}
rv = clk_get_freq(sc->clk, &freq);
if (rv != 0) {
device_printf(dev, "Cannot get clock frequency\n");
goto fail;
}
sc->core_freq = (uint32_t)freq;
rv = clk_enable(sc->clk);
if (rv != 0) {
device_printf(dev, "Cannot enable clock: %d\n", rv);
goto fail;
}
/* Init hardware. */
rv = tegra_i2c_hw_init(sc);
if (rv) {
device_printf(dev, "tegra_i2c_activate failed\n");
goto fail;
}
/* Setup interrupt. */
rv = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
NULL, tegra_i2c_intr, sc, &sc->irq_h);
if (rv) {
device_printf(dev, "Cannot setup interrupt.\n");
goto fail;
}
/* Attach the iicbus. */
sc->iicbus = device_add_child(dev, "iicbus", -1);
if (sc->iicbus == NULL) {
device_printf(dev, "Could not allocate iicbus instance.\n");
rv = ENXIO;
goto fail;
}
/* Probe and attach the iicbus. */
return (bus_generic_attach(dev));
fail:
if (sc->irq_h != NULL)
bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
if (sc->irq_res != NULL)
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
if (sc->mem_res != NULL)
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
LOCK_DESTROY(sc);
return (rv);
}
