static int __init bcmring_clocksource_init(void)
{
/* setup timer1 as free-running clocksource */
writel(0, TIMER1_VA_BASE + TIMER_CTRL);
writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD);
writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE);
writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
TIMER1_VA_BASE + TIMER_CTRL);
clocksource_bcmring_timer1.mult =
clocksource_khz2mult(TIMER1_FREQUENCY_MHZ * 1000,
clocksource_bcmring_timer1.shift);
clocksource_register(&clocksource_bcmring_timer1);
/* setup timer3 as free-running clocksource */
writel(0, TIMER3_VA_BASE + TIMER_CTRL);
writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
TIMER3_VA_BASE + TIMER_CTRL);
clocksource_bcmring_timer3.mult =
clocksource_khz2mult(TIMER3_FREQUENCY_KHZ,
clocksource_bcmring_timer3.shift);
clocksource_register(&clocksource_bcmring_timer3);
return 0;
}
void __init chip_clocksource_init(unsigned int base)
{
struct clocksource *cs = &clocksource_timer;
clksrc_base = base;
#if USE_GLOBAL_TIMER
PERI_W(GT_CONTROL,0x1); //Enable
//calculate the value of mult //cycle= ( time(ns) *mult ) >> shift
cs->mult = clocksource_khz2mult(GLB_TIMER_FREQ_KHZ, cs->shift);//PERICLK = CPUCLK/2
#else
/* setup timer 1 as free-running clocksource */
//make sure timer 1 is disable
CLRREG16(clksrc_base, TIMER_ENABLE);
//set max period
OUTREG16(clksrc_base+(0x2<<2),0xffff);
OUTREG16(clksrc_base+(0x3<<2),0xffff);
//enable timer 1
SETREG16(clksrc_base, TIMER_ENABLE);
// TODO: need to double check
//calculate the value of mult //cycle= ( time(ns) *mult ) >> shift
cs->mult = clocksource_khz2mult(GLB_TIMER_FREQ_KHZ, cs->shift); //Mstar timer =>12Mhz,
#endif
clocksource_register(cs);
}
static void __init davinci_timer_init(void)
{
struct clk *timer_clk;
static char err[] __initdata = KERN_ERR
"%s: can't register clocksource!\n";
/* init timer hw */
timer_init();
timer_clk = clk_get(NULL, "timer0");
BUG_ON(IS_ERR(timer_clk));
clk_enable(timer_clk);
davinci_clock_tick_rate = clk_get_rate(timer_clk);
/* setup clocksource */
clocksource_davinci.mult =
clocksource_khz2mult(davinci_clock_tick_rate/1000,
clocksource_davinci.shift);
if (clocksource_register(&clocksource_davinci))
printk(err, clocksource_davinci.name);
/* setup clockevent */
clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC,
clockevent_davinci.shift);
clockevent_davinci.max_delta_ns =
clockevent_delta2ns(0xfffffffe, &clockevent_davinci);
clockevent_davinci.min_delta_ns =
clockevent_delta2ns(1, &clockevent_davinci);
clockevent_davinci.cpumask = cpumask_of(0);
clockevents_register_device(&clockevent_davinci);
}
static void __init nuc970_clocksource_init(void)
{
unsigned int val;
unsigned int rate = 0;
struct clk *clk = clk_get(NULL, "timer1");
BUG_ON(IS_ERR(clk));
clk_prepare(clk);
clk_enable(clk);
__raw_writel(0x00, REG_TMR_TCSR1);
rate = clk_get_rate(clk) / (PRESCALE + 1);
__raw_writel(0xffffffff, REG_TMR_TICR1);
val = __raw_readl(REG_TMR_TCSR1);
val |= (COUNTEN | PERIOD | PRESCALE);
__raw_writel(val, REG_TMR_TCSR1);
clocksource_nuc970.mult =
clocksource_khz2mult((rate / 1000), clocksource_nuc970.shift);
clocksource_register(&clocksource_nuc970);
}
void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev)
{
struct mlx4_dev *dev = mdev->dev;
u64 ns;
memset(&mdev->cycles, 0, sizeof(mdev->cycles));
mdev->cycles.read = mlx4_en_read_clock;
mdev->cycles.mask = CLOCKSOURCE_MASK(48);
/* Using shift to make calculation more accurate. Since current HW
* clock frequency is 427 MHz, and cycles are given using a 48 bits
* register, the biggest shift when calculating using u64, is 14
* (max_cycles * multiplier < 2^64)
*/
mdev->cycles.shift = 14;
mdev->cycles.mult =
clocksource_khz2mult(1000 * dev->caps.hca_core_clock, mdev->cycles.shift);
timecounter_init(&mdev->clock, &mdev->cycles,
ktime_to_ns(ktime_get_real()));
/* Calculate period in seconds to call the overflow watchdog - to make
* sure counter is checked at least once every wrap around.
*/
ns = cyclecounter_cyc2ns(&mdev->cycles, mdev->cycles.mask);
do_div(ns, NSEC_PER_SEC / 2 / HZ);
mdev->overflow_period = ns;
}
static void __init davinci_timer_init(void)
{
static char err[] __initdata = KERN_ERR
"%s: can't register clocksource!\n";
/* init timer hw */
timer_init();
/* setup clocksource */
clocksource_davinci.mult =
clocksource_khz2mult(CLOCK_TICK_RATE/1000,
clocksource_davinci.shift);
if (clocksource_register(&clocksource_davinci))
printk(err, clocksource_davinci.name);
/* setup clockevent */
clockevent_davinci.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
clockevent_davinci.shift);
clockevent_davinci.max_delta_ns =
clockevent_delta2ns(0xfffffffe, &clockevent_davinci);
clockevent_davinci.min_delta_ns =
clockevent_delta2ns(1, &clockevent_davinci);
clockevent_davinci.cpumask = cpumask_of(0);
clockevents_register_device(&clockevent_davinci);
}
/* Setup free-running counter for clocksource */
static void __init omap2_gp_clocksource_init(void)
{
static struct omap_dm_timer *gpt;
u32 tick_rate, tick_period;
static char err1[] __initdata = KERN_ERR
"%s: failed to request dm-timer\n";
static char err2[] __initdata = KERN_ERR
"%s: can't register clocksource!\n";
gpt = omap_dm_timer_request();
if (!gpt)
printk(err1, clocksource_gpt.name);
gpt_clocksource = gpt;
omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
tick_period = (tick_rate / HZ) - 1;
omap_dm_timer_set_load_start(gpt, 1, 0);
clocksource_gpt.mult =
clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
if (clocksource_register(&clocksource_gpt))
printk(err2, clocksource_gpt.name);
}
static int __init versatile_clocksource_init(void)
{
clocksource_versatile.mult =
clocksource_khz2mult(1000, clocksource_versatile.shift);
clocksource_register(&clocksource_versatile);
return 0;
}
static void __init meson_clocksource_init(void)
{
CLEAR_CBUS_REG_MASK(ISA_TIMER_MUX, TIMER_E_INPUT_MASK);
SET_CBUS_REG_MASK(ISA_TIMER_MUX, TIMERE_UNIT_1ms << TIMER_E_INPUT_BIT);
WRITE_CBUS_REG(ISA_TIMERE, 0);
clocksource_timer_e.shift = clocksource_hz2shift(24, 1000);
clocksource_timer_e.mult =
clocksource_khz2mult(1, clocksource_timer_e.shift);
clocksource_register(&clocksource_timer_e);
}
/*
* timer_device_init()
* Create and init a generic clock driver for Ubicom32.
*/
void timer_device_init(void)
{
int i;
const cpumask_t mask = (CPU_MASK_ALL);
/*
* Get the frequency from the processor device tree node or use
* the default if not available. We will store this as the frequency
* of the timer to avoid future calculations.
*/
frequency = processor_frequency();
if (frequency == 0) {
frequency = CLOCK_TICK_RATE;
}
/*
* Setup the primary clock source around sysval. Linux does not
* supply a Mhz multiplier so convert down to khz.
*/
timer_device_clockbase.mult =
clocksource_khz2mult(frequency / 1000,
timer_device_clockbase.shift);
if (clocksource_register(&timer_device_clockbase)) {
printk(KERN_ERR "timer: clocksource failed to register\n");
return;
}
/*
* Always allocate a primary timer.
*/
timer_device_alloc_event("timer-primary", -1, &mask);
/*
* Initialize the high resolution interface.
*/
timer_device_lock_acquire();
timer_device_high_res = 0;
timer_device_last_sysval = UBICOM32_IO_TIMER->sysval;
timer_device_lock_release();
#if defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
/*
* If BROADCAST is selected we need to add a broadcast timer.
*/
timer_device_alloc_event("timer-broadcast", -1, CPU_MASK_ALL);
#endif
/*
* Allocate extra timers that are requested.
*/
for (i = 0; i < CONFIG_TIMER_EXTRA_ALLOC; i++) {
timer_device_alloc_event("timer-extra", -1, &mask);
}
}
static void __init sec_init_clocksource(unsigned long rate)
{
static char err[] __initdata = KERN_ERR
"%s: can't register clocksource!\n";
clocksource_sec.mult
= clocksource_khz2mult(rate/1000, clocksource_sec.shift);
sec_sched_timer_start(~0, 1);
if (clocksource_register(&clocksource_sec))
printk(err, clocksource_sec.name);
}
static void __init realview_clocksource_init(void)
{
/* setup timer 0 as free-running clocksource */
writel(0, timer3_va_base + TIMER_CTRL);
writel(0xffffffff, timer3_va_base + TIMER_LOAD);
writel(0xffffffff, timer3_va_base + TIMER_VALUE);
writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
timer3_va_base + TIMER_CTRL);
clocksource_realview.mult =
clocksource_khz2mult(1000, clocksource_realview.shift);
clocksource_register(&clocksource_realview);
}
void mlx5e_timestamp_init(struct mlx5e_priv *priv)
{
struct mlx5e_tstamp *tstamp = &priv->tstamp;
u64 ns;
u64 frac = 0;
u32 dev_freq;
mlx5e_timestamp_init_config(tstamp);
dev_freq = MLX5_CAP_GEN(priv->mdev, device_frequency_khz);
if (!dev_freq) {
mlx5_core_warn(priv->mdev, "invalid device_frequency_khz, aborting HW clock init\n");
return;
}
rwlock_init(&tstamp->lock);
tstamp->cycles.read = mlx5e_read_internal_timer;
tstamp->cycles.shift = MLX5E_CYCLES_SHIFT;
tstamp->cycles.mult = clocksource_khz2mult(dev_freq,
tstamp->cycles.shift);
tstamp->nominal_c_mult = tstamp->cycles.mult;
tstamp->cycles.mask = CLOCKSOURCE_MASK(41);
tstamp->mdev = priv->mdev;
timecounter_init(&tstamp->clock, &tstamp->cycles,
ktime_to_ns(ktime_get_real()));
/* Calculate period in seconds to call the overflow watchdog - to make
* sure counter is checked at least once every wrap around.
*/
ns = cyclecounter_cyc2ns(&tstamp->cycles, tstamp->cycles.mask,
frac, &frac);
do_div(ns, NSEC_PER_SEC / 2 / HZ);
tstamp->overflow_period = ns;
INIT_DELAYED_WORK(&tstamp->overflow_work, mlx5e_timestamp_overflow);
if (tstamp->overflow_period)
schedule_delayed_work(&tstamp->overflow_work, 0);
else
mlx5_core_warn(priv->mdev, "invalid overflow period, overflow_work is not scheduled\n");
/* Configure the PHC */
tstamp->ptp_info = mlx5e_ptp_clock_info;
snprintf(tstamp->ptp_info.name, 16, "mlx5 ptp");
tstamp->ptp = ptp_clock_register(&tstamp->ptp_info,
&priv->mdev->pdev->dev);
if (IS_ERR(tstamp->ptp)) {
mlx5_core_warn(priv->mdev, "ptp_clock_register failed %ld\n",
PTR_ERR(tstamp->ptp));
tstamp->ptp = NULL;
}
}
static void __init omap_init_clocksource(unsigned long rate)
{
static char err[] __initdata = KERN_ERR
"%s: can't register clocksource!\n";
clocksource_mpu.mult
= clocksource_khz2mult(rate/1000, clocksource_mpu.shift);
setup_irq(INT_TIMER2, &omap_mpu_timer2_irq);
omap_mpu_timer_start(1, ~0, 1);
if (clocksource_register(&clocksource_mpu))
printk(err, clocksource_mpu.name);
}
void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev)
{
panic("Disabled");
#if 0 // AKAROS_PORT
struct mlx4_dev *dev = mdev->dev;
unsigned long flags;
uint64_t ns, zero = 0;
rwlock_init(&mdev->clock_lock);
memset(&mdev->cycles, 0, sizeof(mdev->cycles));
mdev->cycles.read = mlx4_en_read_clock;
mdev->cycles.mask = CLOCKSOURCE_MASK(48);
/* Using shift to make calculation more accurate. Since current HW
* clock frequency is 427 MHz, and cycles are given using a 48 bits
* register, the biggest shift when calculating using u64, is 14
* (max_cycles * multiplier < 2^64)
*/
mdev->cycles.shift = 14;
mdev->cycles.mult =
clocksource_khz2mult(1000 * dev->caps.hca_core_clock, mdev->cycles.shift);
mdev->nominal_c_mult = mdev->cycles.mult;
write_lock_irqsave(&mdev->clock_lock, flags);
timecounter_init(&mdev->clock, &mdev->cycles,
epoch_nsec());
write_unlock_irqrestore(&mdev->clock_lock, flags);
/* Calculate period in seconds to call the overflow watchdog - to make
* sure counter is checked at least once every wrap around.
*/
ns = cyclecounter_cyc2ns(&mdev->cycles, mdev->cycles.mask, zero, &zero);
do_div(ns, NSEC_PER_SEC / 2 / HZ);
mdev->overflow_period = ns;
/* Configure the PHC */
mdev->ptp_clock_info = mlx4_en_ptp_clock_info;
snprintf(mdev->ptp_clock_info.name, 16, "mlx4 ptp");
mdev->ptp_clock = ptp_clock_register(&mdev->ptp_clock_info,
&mdev->pdev->dev);
if (IS_ERR(mdev->ptp_clock)) {
mdev->ptp_clock = NULL;
mlx4_err(mdev, "ptp_clock_register failed\n");
} else {
mlx4_info(mdev, "registered PHC clock\n");
}
#endif
}
static void __init nuc900_clocksource_init(unsigned int rate)
{
unsigned int val;
__raw_writel(0xffffffff, REG_TICR1);
val = __raw_readl(REG_TCSR1);
val |= (COUNTEN | PERIOD);
__raw_writel(val, REG_TCSR1);
clocksource_nuc900.mult =
clocksource_khz2mult((rate / 1000), clocksource_nuc900.shift);
clocksource_register(&clocksource_nuc900);
}
void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev)
{
struct mlx4_dev *dev = mdev->dev;
unsigned long flags;
u64 ns;
/* mlx4_en_init_timestamp is called for each netdev.
* mdev->ptp_clock is common for all ports, skip initialization if
* was done for other port.
*/
if (mdev->ptp_clock)
return;
rwlock_init(&mdev->clock_lock);
memset(&mdev->cycles, 0, sizeof(mdev->cycles));
mdev->cycles.read = mlx4_en_read_clock;
mdev->cycles.mask = CLOCKSOURCE_MASK(48);
mdev->cycles.shift = freq_to_shift(dev->caps.hca_core_clock);
mdev->cycles.mult =
clocksource_khz2mult(1000 * dev->caps.hca_core_clock, mdev->cycles.shift);
mdev->nominal_c_mult = mdev->cycles.mult;
write_lock_irqsave(&mdev->clock_lock, flags);
timecounter_init(&mdev->clock, &mdev->cycles,
ktime_to_ns(ktime_get_real()));
write_unlock_irqrestore(&mdev->clock_lock, flags);
/* Calculate period in seconds to call the overflow watchdog - to make
* sure counter is checked at least once every wrap around.
*/
ns = cyclecounter_cyc2ns(&mdev->cycles, mdev->cycles.mask);
do_div(ns, NSEC_PER_SEC / 2 / HZ);
mdev->overflow_period = ns;
/* Configure the PHC */
mdev->ptp_clock_info = mlx4_en_ptp_clock_info;
snprintf(mdev->ptp_clock_info.name, 16, "mlx4 ptp");
mdev->ptp_clock = ptp_clock_register(&mdev->ptp_clock_info,
&mdev->pdev->dev);
if (IS_ERR(mdev->ptp_clock)) {
mdev->ptp_clock = NULL;
mlx4_err(mdev, "ptp_clock_register failed\n");
} else {
mlx4_info(mdev, "registered PHC clock\n");
}
}
static int __init versatile_clocksource_init(void)
{
/* setup timer3 as free-running clocksource */
writel(0, TIMER3_VA_BASE + TIMER_CTRL);
writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
TIMER3_VA_BASE + TIMER_CTRL);
clocksource_versatile.mult =
clocksource_khz2mult(1000, clocksource_versatile.shift);
clocksource_register(&clocksource_versatile);
return 0;
}
void __init balong_clocksource_init(void __iomem *base)
{
struct clocksource *cs = &clocksource_balong;
clksrc_base = base;
/* setup timer 9 as free-running clocksource */
writel(0, clksrc_base + TIMER_CTRL);
writel(0xffffffff, clksrc_base + TIMER_LOAD);
writel(TIMER_CTRL_ENABLE | TIMER_CTRL_INTDIS,
clksrc_base + TIMER_CTRL);
cs->mult = clocksource_khz2mult(TIMER_FREQ_KHZ, cs->shift);
clocksource_register(cs);
}
static void __init s5pv310_clocksource_init(void)
{
unsigned long clock_rate;
clock_rate = clk_get_rate(timerclk);
sys_frc_clksrc.mult =
clocksource_khz2mult(clock_rate/1000, sys_frc_clksrc.shift);
s5pv310_systimer_init(SYS_FRC, 0);
s5pv310_systimer_start(SYS_FRC);
if (clocksource_register(&sys_frc_clksrc))
panic("%s: can't register clocksource\n", sys_frc_clksrc.name);
}
static void integrator_clocksource_init(u32 khz)
{
struct clocksource *cs = &clocksource_timersp;
void __iomem *base = clksrc_base;
u32 ctrl = TIMER_CTRL_ENABLE;
if (khz >= 1500) {
khz /= 16;
ctrl = TIMER_CTRL_DIV16;
}
writel(ctrl, base + TIMER_CTRL);
writel(0xffff, base + TIMER_LOAD);
cs->mult = clocksource_khz2mult(khz, cs->shift);
clocksource_register(cs);
}
static int __init init_vmi_clocksource(void)
{
cycle_t cycles_per_msec;
if (!vmi_timer_ops.get_cycle_frequency)
return 0;
/* Use khz2mult rather than hz2mult since hz arg is only 32-bits. */
cycles_per_msec = vmi_timer_ops.get_cycle_frequency();
(void)do_div(cycles_per_msec, 1000);
/* Note that clocksource.{mult, shift} converts in the opposite direction
* as clockevents. */
clocksource_vmi.mult = clocksource_khz2mult(cycles_per_msec,
clocksource_vmi.shift);
printk(KERN_WARNING "vmi: registering clock source khz=%lld\n", cycles_per_msec);
return clocksource_register(&clocksource_vmi);
}
static void __init s5pv310_clocksource_init(void)
{
unsigned long pclk;
unsigned long clock_rate;
pclk = clk_get_rate(timerclk);
clk_set_rate(tdiv4, pclk / 2);
clk_set_parent(tin4, tdiv4);
clock_rate = clk_get_rate(tin4);
s5pv310_pwm_init(4, ~0);
s5pv310_pwm_start(4, 1);
pwm_clocksource.mult =
clocksource_khz2mult(clock_rate/1000, pwm_clocksource.shift);
if (clocksource_register(&pwm_clocksource))
panic("%s: can't register clocksource\n", pwm_clocksource.name);
}
static void __init meson_clocksource_init(void)
{
CLEAR_CBUS_REG_MASK(ISA_TIMER_MUX, TIMER_E_INPUT_MASK);
SET_CBUS_REG_MASK(ISA_TIMER_MUX, TIMERE_UNIT_1ms << TIMER_E_INPUT_BIT);
WRITE_CBUS_REG(ISA_TIMERE, 0);
clocksource_timer_e.shift = clocksource_hz2shift(24, 1000);
clocksource_timer_e.mult =
clocksource_khz2mult(1, clocksource_timer_e.shift);
clocksource_timer_f.shift = clocksource_timer_e.shift;
//clocksource_timer_f.mult = ((clocksource_timer_e.mult)>>6)*64;
clocksource_timer_f.mult = ((clocksource_timer_e.mult)>>6)*40;
/*printk("Timer-E=%x,%x, Timer-F=%x,%x",
clocksource_timer_e.shift,
clocksource_timer_e.mult,
clocksource_timer_f.shift,
clocksource_timer_f.mult
);*/
clocksource_register(&clocksource_timer_e);
clocksource_register(&clocksource_timer_f);
}
static void __init u300_timer_init(void)
{
u300_enable_timer_clock();
/*
* Disable the "OS" and "DD" timers - these are designed for Symbian!
* Example usage in cnh1601578 cpu subsystem pd_timer_app.c
*/
writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
writel(U300_TIMER_APP_ROST_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
writel(U300_TIMER_APP_RDDT_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
/* Reset the General Purpose timer 1. */
writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
/* Set up the IRQ handler */
setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
/* Reset the General Purpose timer 2 */
writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
/* Set this timer to run around forever */
writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
/* Set continuous mode so it wraps around */
writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
/* Disable timer interrupts */
writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
/* Then enable the GP2 timer to use as a free running us counter */
writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
/* This is a pure microsecond clock source */
clocksource_u300_1mhz.mult =
clocksource_khz2mult(1000, clocksource_u300_1mhz.shift);
if (clocksource_register(&clocksource_u300_1mhz))
printk(KERN_ERR "timer: failed to initialize clock "
"source %s\n", clocksource_u300_1mhz.name);
clockevent_u300_1mhz.mult =
div_sc(1000000, NSEC_PER_SEC, clockevent_u300_1mhz.shift);
/* 32bit counter, so 32bits delta is max */
clockevent_u300_1mhz.max_delta_ns =
clockevent_delta2ns(0xffffffff, &clockevent_u300_1mhz);
/* This timer is slow enough to set for 1 cycle == 1 MHz */
clockevent_u300_1mhz.min_delta_ns =
clockevent_delta2ns(1, &clockevent_u300_1mhz);
clockevent_u300_1mhz.cpumask = cpumask_of(0);
clockevents_register_device(&clockevent_u300_1mhz);
/*
* TODO: init and register the rest of the timers too, they can be
* used by hrtimers!
*/
}
