static void i82801cx_rtc_init(struct device *dev)
{
uint32_t dword;
int rtc_failed;
int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
if (rtc_failed) {
// Clear the RTC_BATTERY_DEAD bit, but preserve
// the RTC_POWER_FAILED, G3 state, and reserved bits
// NOTE: RTC_BATTERY_DEAD and RTC_POWER_FAILED are "write-1-clear" bits
pmcon3 &= ~RTC_POWER_FAILED;
}
get_option(&pwr_on, "power_on_after_fail");
pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
if (!pwr_on) {
pmcon3 |= SLEEP_AFTER_POWER_FAIL;
}
pci_write_config8(dev, GEN_PMCON_3, pmcon3);
printk(BIOS_INFO, "set power %s after power fail\n",
pwr_on ? "on" : "off");
// See if the Safe Mode jumper is set
dword = pci_read_config32(dev, GEN_STS);
rtc_failed |= dword & (1 << 2);
cmos_init(rtc_failed);
}
static void lpc_init(device_t dev)
{
/* Initialize the real time clock */
cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
}
static void lpc_init(device_t dev)
{
u8 byte;
u32 dword;
device_t sm_dev;
/* Enable the LPC Controller */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
dword = pci_read_config32(sm_dev, 0x64);
dword |= 1 << 20;
pci_write_config32(sm_dev, 0x64, dword);
/* Initialize isa dma */
isa_dma_init();
/* Enable DMA transaction on the LPC bus */
byte = pci_read_config8(dev, 0x40);
byte |= (1 << 2);
pci_write_config8(dev, 0x40, byte);
/* Disable the timeout mechanism on LPC */
byte = pci_read_config8(dev, 0x48);
byte &= ~(1 << 7);
pci_write_config8(dev, 0x48, byte);
/* Disable LPC MSI Capability */
byte = pci_read_config8(dev, 0x78);
byte &= ~(1 << 1);
byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going
on on LPC, it holds PCI grant, so no LPC slave cycle can
interrupt and visit LPC. */
pci_write_config8(dev, 0x78, byte);
/* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */
/* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */
byte = pci_read_config8(dev, 0xBB);
byte |= 1 << 0 | 1 << 3;
pci_write_config8(dev, 0xBB, byte);
cmos_check_update_date();
/* Initialize the real time clock.
* The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
* 1 tells cmos_init to always initialize the CMOS.
*/
cmos_init(0);
/* Initialize i8259 pic */
setup_i8259 ();
/* Initialize i8254 timers */
setup_i8254 ();
}
/*
* Preserve Vboot NV data when clearing CMOS as it will
* have been re-initialized already by Vboot firmware init.
*/
static void pch_cmos_init_preserve(int reset)
{
uint8_t vbnv[VBNV_BLOCK_SIZE];
if (reset)
read_vbnv(vbnv);
cmos_init(reset);
if (reset)
save_vbnv(vbnv);
}
void init_vbnv_cmos(int rtc_fail)
{
uint8_t vbnv[VBOOT_VBNV_BLOCK_SIZE];
if (rtc_fail)
read_vbnv_cmos(vbnv);
cmos_init(rtc_fail);
if (rtc_fail)
save_vbnv_cmos(vbnv);
}
void sb_rtc_init(void)
{
int rtc_failed = rtc_failure();
if (rtc_failed) {
if (IS_ENABLED(CONFIG_ELOG))
elog_add_event(ELOG_TYPE_RTC_RESET);
pci_update_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3,
~RTC_BATTERY_DEAD, 0);
}
printk(BIOS_DEBUG, "RTC: failed = 0x%x\n", rtc_failed);
cmos_init(rtc_failed);
}
static void i82801gx_rtc_init(struct device *dev)
{
u8 reg8;
int rtc_failed;
reg8 = pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
cmos_init(rtc_failed);
}
static void baytrail_rtc_init(void)
{
uint32_t *pbase = (uint32_t *)(pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0);
uint32_t gen_pmcon1 = read32(pbase + (GEN_PMCON1/sizeof(u32)));
int rtc_failed = !!(gen_pmcon1 & RPS);
if (rtc_failed) {
printk(BIOS_DEBUG,
"RTC Failure detected. Resetting Date to %s\n",
coreboot_dmi_date);
write32((uint32_t *)(DEFAULT_PBASE + GEN_PMCON1), gen_pmcon1 & ~RPS);
}
cmos_init(rtc_failed);
}
static void lpc_init(struct device *dev)
{
uint8_t byte;
int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
i82801ex_general_cntl(dev);
/* IO APIC initialization. */
setup_ioapic(VIO_APIC_VADDR, 0); // Don't rename IO APIC ID.
i82801ex_enable_serial_irqs(dev);
i82801ex_pci_dma_cfg(dev);
i82801ex_enable_lpc(dev);
/* Clear SATA to non raid */
pci_write_config8(dev, 0xae, 0x00);
get_option(&pwr_on, "power_on_after_fail");
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
if (!pwr_on) {
byte |= 1;
}
pci_write_config8(dev, 0xa4, byte);
printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
/* Set up the PIRQ */
i82801ex_pirq_init(dev);
/* Set the state of the gpio lines */
i82801ex_gpio_init(dev);
/* Initialize the real time clock */
cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
/* Disable IDE (needed when sata is enabled) */
pci_write_config8(dev, 0xf2, 0x60);
enable_hpet(dev);
}
static void rtc_init(void)
{
int rtc_fail;
const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
if (!ps) {
printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n");
return;
}
rtc_fail = !!(ps->gen_pmcon1 & RPS);
/* Ensure the date is set including century byte. */
cmos_check_update_date();
if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS))
init_vbnv_cmos(rtc_fail);
else
cmos_init(rtc_fail);
}
static void pch_rtc_init(struct device *dev)
{
u8 reg8;
int rtc_failed;
reg8 = pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
#if CONFIG_ELOG
elog_add_event(ELOG_TYPE_RTC_RESET);
#endif
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
cmos_init(rtc_failed);
}
static void pch_rtc_init(struct device *dev)
{
u8 reg8;
int rtc_failed;
reg8 = pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
}
if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS))
init_vbnv_cmos(rtc_failed);
else
cmos_init(rtc_failed);
}
static void lpc_init(device_t dev)
{
printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n");
cmos_check_update_date();
/* Initialize the real time clock.
* The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
* 1 tells cmos_init to always initialize the CMOS.
*/
cmos_init(0);
setup_i8259(); /* Initialize i8259 pic */
setup_i8254(); /* Initialize i8254 timers */
printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - End.\n");
}
static void reset_rtc(void)
{
uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) &
0xfffffff0;
uint32_t gen_pmcon1 = read32((void *)(pbase + GEN_PMCON1));
int rtc_failed = !!(gen_pmcon1 & RPS);
if (rtc_failed) {
printk(BIOS_DEBUG,
"RTC Failure detected. Resetting Date to %s\n",
coreboot_dmi_date);
/* Clear the power failure flag */
write32((void *)(DEFAULT_PBASE + GEN_PMCON1),
gen_pmcon1 & ~RPS);
}
cmos_init(rtc_failed);
}
static void i82801ax_rtc_init(struct device *dev)
{
uint8_t reg8;
uint32_t reg32;
int rtc_failed;
reg8 = pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {
reg8 &= ~(1 << 1); /* Preserve the power fail state. */
pci_write_config8(dev, GEN_PMCON_3, reg8);
}
reg32 = pci_read_config32(dev, GEN_STA);
rtc_failed |= reg32 & (1 << 2);
cmos_init(rtc_failed);
/* Enable access to the upper 128 byte bank of CMOS RAM. */
pci_write_config8(dev, RTC_CONF, 0x04);
}
static void sc_rtc_init(void)
{
uint32_t gen_pmcon1;
int rtc_fail;
struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
printk(BIOS_SPEW, "%s/%s\n",
__FILE__, __func__);
if (ps != NULL)
gen_pmcon1 = ps->gen_pmcon1;
else
gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1));
rtc_fail = !!(gen_pmcon1 & RPS);
if (rtc_fail)
printk(BIOS_DEBUG, "RTC failure.\n");
cmos_init(rtc_fail);
}
static void pch_rtc_init(void)
{
u8 reg8;
int rtc_failed;
/*PMC Controller Device 0x1F, Func 02*/
device_t dev = PCH_DEV_PMC;
reg8 = pci_read_config8(dev, GEN_PMCON_B);
rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_B, reg8);
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
}
#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
pch_cmos_init_preserve(rtc_failed);
#else
cmos_init(rtc_failed);
#endif
}
int main()
{
//Start video driver (must always be before loading message)
mm_init();
pg_init();
real_init();
video_init();
video_setdriver(video_vgatext_getdriver(),0);
//Put loading message
cli_puts("ArcaneOS Loading...\n");
//Setup kernel
gdt_init();
idt_init();
isr_init();
irq_init();
timer_init();
kb_init();
ui_init();
cpuid_init();
cmos_init();
rtc_init();
acpi_init();
power_init();
mt_init();
syscall_init();
floppy_init();
__asm__ __volatile__ ("sti");
//Enable ACPI
acpi_enable();
//Create thread for ui
mt_create_thread(mt_kernel_process,test,2);
//Endless loop to prevent bugs when all threads are sleeping
for(;;)
__asm__ __volatile__ ("hlt");
}
static void pch_rtc_init(void)
{
u8 reg8;
int rtc_failed;
/*PMC Controller Device 0x1F, Func 02*/
device_t dev = PCH_DEV_PMC;
reg8 = pci_read_config8(dev, GEN_PMCON_B);
rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_B, reg8);
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
}
/* Ensure the date is set including century byte. */
cmos_check_update_date();
if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS))
init_vbnv_cmos(rtc_failed);
else
cmos_init(rtc_failed);
}
static void lpc_init(device_t dev)
{
uint8_t byte;
uint8_t byte_old;
int on;
int nmi_option;
printk(BIOS_DEBUG, "LPC_INIT -------->\n");
pc_keyboard_init();
lpc_usb_legacy_init(dev);
lpc_common_init(dev);
/* power after power fail */
on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on) {
byte |= 0x40;
}
pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
if(on) {
uint16_t pm10_bar;
uint32_t dword;
pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
dword = inl(pm10_bar + 0x10);
on = 8-on;
printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
(on*12)+(on>>1),(on&1)*5);
}
/* Enable Error reporting */
/* Set up sync flood detected */
byte = pci_read_config8(dev, 0x47);
byte |= (1 << 1);
pci_write_config8(dev, 0x47, byte);
/* Set up NMI on errors */
byte = inb(0x70); // RTC70
byte_old = byte;
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
} else {
byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
}
if( byte != byte_old) {
outb(byte, 0x70);
}
/* Initialize the real time clock */
cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
printk(BIOS_DEBUG, "LPC_INIT <--------\n");
}
/*
* SB700 enables all USB controllers by default in SMBUS Control.
* SB700 enables SATA by default in SMBUS Control.
*/
static void sm_init(device_t dev)
{
u8 byte;
u8 byte_old;
u8 rev;
u32 dword;
void *ioapic_base;
uint32_t power_state;
uint32_t enable_legacy_usb;
u32 nmi_option;
printk(BIOS_INFO, "sm_init().\n");
rev = get_sb700_revision(dev);
/* This works in a similar fashion to a memory resource, but without an enable bit */
ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0));
setup_ioapic(ioapic_base, 0); /* Don't rename IOAPIC ID. */
enable_legacy_usb = 1;
get_option(&enable_legacy_usb, "enable_legacy_usb");
/* 2.10 Interrupt Routing/Filtering */
byte = pci_read_config8(dev, 0x62);
if (enable_legacy_usb)
byte |= 0x3;
else
byte &= ~0x3;
pci_write_config8(dev, 0x62, byte);
byte = pci_read_config8(dev, 0x67);
if (enable_legacy_usb)
byte |= 0x1 << 7;
else
byte &= ~(0x1 << 7);
pci_write_config8(dev, 0x67, byte);
/* Delay back to back interrupts to the CPU. */
dword = pci_read_config16(dev, 0x64);
dword |= 1 << 13;
pci_write_config16(dev, 0x64, dword);
/* rrg:K8 INTR Enable (BIOS should set this bit after PIC initialization) */
/* rpr 2.1 Enabling Legacy Interrupt */
dword = pci_read_config8(dev, 0x62);
dword |= 1 << 2;
pci_write_config8(dev, 0x62, dword);
dword = pci_read_config32(dev, 0x78);
dword |= 1 << 9;
pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */
/* bit 10: MultiMediaTimerIrqEn */
dword = pci_read_config8(dev, 0x64);
dword |= 1 << 10;
pci_write_config8(dev, 0x64, dword);
/* enable serial irq */
byte = pci_read_config8(dev, 0x69);
byte |= 1 << 7; /* enable serial irq function */
byte &= ~(0xF << 2);
byte |= 4 << 2; /* set NumSerIrqBits=4 */
pci_write_config8(dev, 0x69, byte);
/* Sx State Settings
* Note: These 2 registers need to be set correctly for the S-state
* to work properly. Otherwise the system may hang during resume
* from the S-state.
*/
/*Use 8us clock for delays in the S-state resume timing sequence.*/
byte = pm_ioread(0x65);
byte &= ~(1 << 7);
pm_iowrite(0x65, byte);
/* Delay the APIC interrupt to the CPU until the system has fully resumed from the S-state. */
byte = pm_ioread(0x68);
byte |= 1 << 2;
pm_iowrite(0x68, byte);
/* IRQ0From8254 */
byte = pci_read_config8(dev, 0x41);
byte &= ~(1 << 7);
pci_write_config8(dev, 0x41, byte);
byte = pm_ioread(0x61);
if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
byte &= ~(1 << 1); /* Clear for non-K8 CPUs */
else
byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
pm_iowrite(0x61, byte);
/* disable SMI */
byte = pm_ioread(0x53);
byte |= 1 << 3;
pm_iowrite(0x53, byte);
/* power after power fail */
power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&power_state, "power_on_after_fail");
if (power_state > 2) {
printk(BIOS_WARNING, "Invalid power_on_after_fail setting, using default\n");
power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
}
byte = pm_ioread(0x74);
byte &= ~0x03;
if (power_state == POWER_MODE_OFF)
byte |= 0x0;
else if (power_state == POWER_MODE_ON)
byte |= 0x1;
else if (power_state == POWER_MODE_LAST)
byte |= 0x2;
byte |= 1 << 2;
pm_iowrite(0x74, byte);
printk(BIOS_INFO, "set power \"%s\" after power fail\n", power_mode_names[power_state]);
byte = pm_ioread(0x68);
byte &= ~(1 << 1);
/* 2.7 */
byte |= 1 << 2;
pm_iowrite(0x68, byte);
/* 2.7 */
byte = pm_ioread(0x65);
byte &= ~(1 << 7);
pm_iowrite(0x65, byte);
/* 2.16 */
byte = pm_ioread(0x55);
byte |= 1 << 5;
pm_iowrite(0x55, byte);
byte = pm_ioread(0xD7);
byte |= 1 << 6 | 1 << 1;
pm_iowrite(0xD7, byte);
/* 2.15 */
byte = pm_ioread(0x42);
byte &= ~(1 << 2);
pm_iowrite(0x42, byte);
/* Set up NMI on errors */
byte = inb(0x70); /* RTC70 */
byte_old = byte;
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
printk(BIOS_INFO, "++++++++++set NMI+++++\n");
} else {
byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */
printk(BIOS_INFO, "++++++++++no set NMI+++++\n");
}
byte &= ~(1 << 7);
if (byte != byte_old) {
outb(byte, 0x70);
}
/*rpr v2.13 2.22 SMBUS PCI Config */
byte = pci_read_config8(dev, 0xE1);
if ((REV_SB700_A11 == rev) || REV_SB700_A12 == rev) {
byte |= 1 << 0;
}
/*Set bit2 to 1, enable Io port 60h read/write SMi trapping and
*Io port 64h write Smi trapping. conflict with ps2 keyboard
*/
//byte |= 1 << 2 | 1 << 3 | 1 << 4;
byte |= 1 << 3 | 1 << 4;
pci_write_config8(dev, 0xE1, byte);
/* 2.5 Enabling Non-Posted Memory Write */
axindxc_reg(0x10, 1 << 9, 1 << 9);
/* 2.11 IO Trap Settings */
abcfg_reg(0x10090, 1 << 16, 1 << 16);
/* ab index */
pci_write_config32(dev, 0xF0, AB_INDX);
/* Initialize the real time clock */
cmos_init(0);
/* 4.3 Enabling Upstream DMA Access */
axcfg_reg(0x04, 1 << 2, 1 << 2);
/* 4.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
abcfg_reg(0x10060, 9 << 17, 9 << 17);
abcfg_reg(0x10064, 9 << 17, 9 << 17);
/* 4.5 Enabling OHCI Prefetch for Performance Enhancement, A12 */
abcfg_reg(0x80, 1 << 0, 1<< 0);
/* 4.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */
/* 4.7 Enabling Additional Address Bits Checking in Downstream */
/* 4.16 IO write and SMI ordering enhancement*/
abcfg_reg(0x9c, 3 << 0, 3 << 0);
if (REV_SB700_A12 == rev) {
abcfg_reg(0x9c, 1 << 8, 1 << 8);
} else if (rev >= REV_SB700_A14) {
abcfg_reg(0x9c, 1 << 8, 0 << 8);
}
if (REV_SB700_A15 == rev) {
abcfg_reg(0x90, 1 << 21, 1 << 21);
abcfg_reg(0x9c, 1 << 5 | 1 << 9 | 1 << 15, 1 << 5 | 1 << 9 | 1 << 15);
}
/* 4.8 Set B-Link Prefetch Mode */
abcfg_reg(0x80, 3 << 17, 3 << 17);
/* 4.9 Enabling Detection of Upstream Interrupts */
abcfg_reg(0x94, 1 << 20 | 0x7FFFF, 1 << 20 | 0x00FEE);
/* 4.10: Enabling Downstream Posted Transactions to Pass Non-Posted
* Transactions for the K8 Platform (for All Revisions) */
abcfg_reg(0x10090, 1 << 8, 1 << 8);
/* Set ACPI Software clock Throttling Period to 244 us*/
byte = pm_ioread(0x68);
byte &= ~(3 << 6);
byte |= (2 << 6); /* 244us */
pm_iowrite(0x68, byte);
if (REV_SB700_A15 == rev) {
u16 word;
/* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */
axindxc_reg(0x02, 1 << 9, 1 << 9);
abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0);
abcfg_reg(0x1009C, 0x00000030, 0x00000030);
abcfg_reg(0x10090, 0x00001E00, 0x00001E00);
/* rpr v2.13 4.19 Enabling Posted Pass Non-Posted Upstream */
abcfg_reg(0x58, 0x0000F800, 0x0000E800);
/* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */
axindxc_reg(0x02, 1 << 10, 1 << 10);
/* rpr v2.13 2.38 Unconditional Shutdown */
byte = pci_read_config8(dev, 0x43);
byte &= ~(1 << 3);
pci_write_config8(dev, 0x43, byte);
word = pci_read_config16(dev, 0x38);
word |= 1 << 12;
pci_write_config16(dev, 0x38, word);
byte |= 1 << 3;
pci_write_config8(dev, 0x43, byte);
/* Enable southbridge MMIO decode */
dword = pci_read_config32(dev, SB_MMIO_CFG_REG);
dword &= ~(0xffffff << 8);
dword |= SB_MMIO_BASE_ADDRESS;
dword |= 0x1;
pci_write_config32(dev, SB_MMIO_CFG_REG, dword);
}
byte = pci_read_config8(dev, 0xAE);
if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID))
byte |= 1 << 4;
byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */
byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */
pci_write_config8(dev, 0xAE, byte);
/* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */
/* 4.12: Enabling AB and BIF Clock Gating */
abcfg_reg(0x10054, 0xFFFF0000, 0x1040000);
abcfg_reg(0x54, 0xFF << 16, 4 << 16);
abcfg_reg(0x54, 1 << 24, 0 << 24);
abcfg_reg(0x98, 0x0000FF00, 0x00004700);
/* 4.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */
abcfg_reg(0x10054, 0x0000FFFF, 0x07FF);
/* 4.14:Enabling Requester ID for upstream traffic. */
abcfg_reg(0x98, 1 << 16, 1 << 16);
/* 9.2: Enabling IDE Data Bus DD7 Pull Down Resistor */
byte = pm2_ioread(0xE5);
byte |= 1 << 2;
pm2_iowrite(0xE5, byte);
/* Enable IDE controller. */
byte = pm_ioread(0x59);
byte &= ~(1 << 1);
pm_iowrite(0x59, byte);
/* Enable SCI as irq9. */
outb(0x4, 0xC00);
outb(0x9, 0xC01);
printk(BIOS_INFO, "sm_init() end\n");
/* Enable NbSb virtual channel */
axcfg_reg(0x114, 0x3f << 1, 0 << 1);
axcfg_reg(0x120, 0x7f << 1, 0x7f << 1);
axcfg_reg(0x120, 7 << 24, 1 << 24);
axcfg_reg(0x120, 1 << 31, 1 << 31);
abcfg_reg(0x50, 1 << 3, 1 << 3);
}
/* This looks good enough to work, maybe */
static void vx800_sb_init(struct device *dev)
{
unsigned char enables;
// enable the internal I/O decode
enables = pci_read_config8(dev, 0x6C);
enables |= 0x80;
pci_write_config8(dev, 0x6C, enables);
// Map 4MB of FLASH into the address space
// pci_write_config8(dev, 0x41, 0x7f);
// Set bit 6 of 0x40, because Award does it (IO recovery time)
// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
// interrupts can be properly marked as level triggered.
enables = pci_read_config8(dev, 0x40);
enables |= 0x44;
pci_write_config8(dev, 0x40, enables);
/* DMA Line buffer control */
enables = pci_read_config8(dev, 0x42);
enables |= 0xf0;
pci_write_config8(dev, 0x42, enables);
/* I/O recovery time */
pci_write_config8(dev, 0x4c, 0x44);
/* ROM memory cycles go to LPC. */
pci_write_config8(dev, 0x59, 0x80);
/* Set 0x5b to 0x01 to match Award */
//pci_write_config8(dev, 0x5b, 0x01);
enables = pci_read_config8(dev, 0x5b);
enables |= 0x01;
pci_write_config8(dev, 0x5b, enables);
/* Set Read Pass Write Control Enable */
pci_write_config8(dev, 0x48, 0x0c);
/* Set 0x58 to 0x42 APIC and RTC. */
//pci_write_config8(dev, 0x58, 0x42); this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0.
enables = pci_read_config8(dev, 0x58);
enables |= 0x41; //
pci_write_config8(dev, 0x58, enables);
/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
enables = pci_read_config8(dev, 0x4f);
enables |= 0x08;
pci_write_config8(dev, 0x4f, enables);
/* enable serial irq */
pci_write_config8(dev, 0x52, 0x9);
/* dma */
pci_write_config8(dev, 0x53, 0x00);
// Power management setup
setup_pm(dev);
/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
pci_write_config8(dev, 0x40, 0x54);
// Start the rtc
cmos_init(0);
}
/*
* SB600 enables all USB controllers by default in SMBUS Control.
* SB600 enables SATA by default in SMBUS Control.
*/
static void sm_init(device_t dev)
{
u8 byte;
u8 byte_old;
u32 dword;
u32 ioapic_base;
u32 on;
u32 nmi_option;
printk(BIOS_INFO, "sm_init().\n");
ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */
/* Don't rename APIC ID */
clear_ioapic(ioapic_base);
dword = pci_read_config8(dev, 0x62);
dword |= 1 << 2;
pci_write_config8(dev, 0x62, dword);
dword = pci_read_config32(dev, 0x78);
dword |= 1 << 9;
pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */
/* bit 10: MultiMediaTimerIrqEn */
dword = pci_read_config8(dev, 0x64);
dword |= 1 << 10;
pci_write_config8(dev, 0x64, dword);
/* enable serial irq */
byte = pci_read_config8(dev, 0x69);
byte |= 1 << 7; /* enable serial irq function */
byte &= ~(0xF << 2);
byte |= 4 << 2; /* set NumSerIrqBits=4 */
pci_write_config8(dev, 0x69, byte);
byte = pm_ioread(0x61);
byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
pm_iowrite(0x61, byte);
/* disable SMI */
byte = pm_ioread(0x53);
byte |= 1 << 3;
pm_iowrite(0x53, byte);
/* power after power fail */
on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
byte = pm_ioread(0x74);
byte &= ~0x03;
if (on) {
byte |= 1 << 0;
}
byte |= 1 << 2;
pm_iowrite(0x74, byte);
printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
/* sb600 rpr:2.3.3: */
byte = pm_ioread(0x9A);
byte |= 1 << 5 | 1 << 4 | 1 << 2;
pm_iowrite(0x9A, byte);
byte = pm_ioread(0x8F);
byte |= 1 << 5;
byte &= ~(1 << 4);
pm_iowrite(0x8F, byte);
pm_iowrite(0x8B, 0x01);
pm_iowrite(0x8A, 0x90);
pm_iowrite(0x88, 0x10); /* A21 */
byte = pm_ioread(0x7C);
byte |= 1 << 0;
pm_iowrite(0x7C, byte);
byte = pm_ioread(0x68);
byte &= ~(1 << 1);
/* 2.6 */
byte |= 1 << 2;
pm_iowrite(0x68, byte);
/* 2.6 */
byte = pm_ioread(0x65);
byte &= ~(1 << 7);
pm_iowrite(0x65, byte);
/* 2.3.4 */
byte = pm_ioread(0x52);
byte &= ~0x2F;
byte |= 0x8;
pm_iowrite(0x52, byte);
byte = pm_ioread(0x8D);
byte &= ~(1 << 6);
pm_iowrite(0x8D, byte);
byte = pm_ioread(0x61);
byte &= ~(1 << 2);
pm_iowrite(0x61, byte);
byte = pm_ioread(0x42);
byte &= ~(1 << 2);
pm_iowrite(0x42, byte);
/* Set up NMI on errors */
byte = inb(0x70); /* RTC70 */
byte_old = byte;
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
printk(BIOS_INFO, "++++++++++set NMI+++++\n");
} else {
byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */
printk(BIOS_INFO, "++++++++++no set NMI+++++\n");
}
byte &= ~(1 << 7);
if (byte != byte_old) {
outb(byte, 0x70);
}
/* 2.10 IO Trap Settings */
abcfg_reg(0x10090, 1 << 16, 1 << 16);
/* ab index */
pci_write_config32(dev, 0xF0, AB_INDX);
/* Initialize the real time clock */
cmos_init(0);
/*3.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
abcfg_reg(0x10060, 9 << 17, 9 << 17);
abcfg_reg(0x10064, 9 << 17, 9 << 17);
/* 3.5 Enabling OHCI Prefetch for Performance Enhancement */
abcfg_reg(0x80, 1 << 0, 1<< 0);
/* 3.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */
/* 3.7 Enabling Additional Address Bits Checking in Downstream */
abcfg_reg(0x9c, 3 << 0, 3 << 0);
/* 3.8 Set B-Link Prefetch Mode */
abcfg_reg(0x80, 3 << 17, 3 << 17);
/* 3.9 Enabling Detection of Upstream Interrupts */
abcfg_reg(0x94, 1 << 20,1 << 20);
/* 3.10: Enabling Downstream Posted Transactions to Pass Non-Posted
* Transactions for the K8 Platform (for All Revisions) */
abcfg_reg(0x10090, 1 << 8, 1 << 8);
/* 3.11:Programming Cycle Delay for AB and BIF Clock Gating */
/* 3.12: Enabling AB and BIF Clock Gating */
abcfg_reg(0x10054, 0xFFFF0000, 0x1040000);
abcfg_reg(0x54, 0xFF << 16, 4 << 16);
printk(BIOS_INFO, "3.11, ABCFG:0x54\n");
abcfg_reg(0x54, 1 << 24, 1 << 24);
printk(BIOS_INFO, "3.12, ABCFG:0x54\n");
abcfg_reg(0x98, 0x0000FF00, 0x00004700);
/* 3.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */
abcfg_reg(0x10054, 0x0000FFFF, 0x07FF);
/* 3.14:Enabling L1 on A-link Express */
axcfg_reg(0x68, 0x00000003, 0x2);
axindxp_reg(0xa0, 0x0000F000, 0x6000);
abcfg_reg(0x10098, 0xFFFFFFFF, 0x4000);
abcfg_reg(0x04, 0xFFFFFFFF, 0x6);
printk(BIOS_INFO, "sm_init() end\n");
/* Enable NbSb virtual channel */
axcfg_reg(0x114, 0x3f << 1, 0 << 1);
axcfg_reg(0x120, 0x7f << 1, 0x7f << 1);
axcfg_reg(0x120, 7 << 24, 1 << 24);
axcfg_reg(0x120, 1 << 31, 1 << 31);
abcfg_reg(0x50, 1 << 3, 1 << 3);
}
