void __init exynos4_init_irq(void)
{
	int irq;

	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;

	gic_init(0, IRQ_PPI_MCT_L, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
	gic_arch_extn.irq_set_wake = s3c_irq_wake;

	for (irq = 0; irq < COMMON_COMBINER_NR; irq++) {
		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
				COMBINER_IRQ(irq, 0));
		combiner_cascade_irq(irq, COMBINER_MAP(irq));
	}

	if (soc_is_exynos4412() && (samsung_rev() >= EXYNOS4412_REV_1_0)) {
		for (irq = COMMON_COMBINER_NR; irq < MAX_COMBINER_NR; irq++) {
			combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
					COMBINER_IRQ(irq, 0));
			combiner_cascade_irq(irq, COMBINER_MAP(irq));
		}
	}

	/* The parameters of s5p_init_irq() are for VIC init.
	 * Theses parameters should be NULL and 0 because EXYNOS4
	 * uses GIC instead of VIC.
	 */
	s5p_init_irq(NULL, 0);
}
Exemplo n.º 2
0
void __init exynos4_init_irq(void)
{
	int irq;
	unsigned int gic_bank_offset;

	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;

	if (!of_have_populated_dt())
		gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
#ifdef CONFIG_OF
	else
		of_irq_init(exynos4_dt_irq_match);
#endif

	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {

		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
				COMBINER_IRQ(irq, 0));
		combiner_cascade_irq(irq, IRQ_SPI(irq));
	}

	/*
	 * The parameters of s5p_init_irq() are for VIC init.
	 * Theses parameters should be NULL and 0 because EXYNOS4
	 * uses GIC instead of VIC.
	 */
	s5p_init_irq(NULL, 0);
}
Exemplo n.º 3
0
static int __init combiner_of_init(struct device_node *np,
				   struct device_node *parent)
{
	void __iomem *combiner_base;
	unsigned int max_nr = 20;
	int irq_base = -1;

	combiner_base = of_iomap(np, 0);
	if (!combiner_base) {
		pr_err("%s: failed to map combiner registers\n", __func__);
		return -ENXIO;
	}

	if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
		pr_info("%s: number of combiners not specified, "
			"setting default as %d.\n",
			__func__, max_nr);
	}

	/* 
	 * FIXME: This is a hardwired COMBINER_IRQ(0,0). Once all devices
	 * get their IRQ from DT, remove this in order to get dynamic
	 * allocation.
	 */
	irq_base = 160;

	combiner_init(combiner_base, np, max_nr, irq_base);

	return 0;
}
Exemplo n.º 4
0
Arquivo: common.c Projeto: 08opt/linux
void __init exynos4_init_irq(void)
{
	int irq;

	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;

	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
	gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
	gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
	gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;

	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {

		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
				COMBINER_IRQ(irq, 0));
		combiner_cascade_irq(irq, IRQ_SPI(irq));
	}

	/*
	 * The parameters of s5p_init_irq() are for VIC init.
	 * Theses parameters should be NULL and 0 because EXYNOS4
	 * uses GIC instead of VIC.
	 */
	s5p_init_irq(NULL, 0);
}
Exemplo n.º 5
0
void __init s5pv310_init_irq(void)
{
	int irq;

#ifdef CONFIG_USE_EXT_GIC
	gic_cpu_base_addr = S5P_VA_EXTGIC_CPU;
	gic_dist_init(0, S5P_VA_EXTGIC_DIST, IRQ_SPI(0));
	gic_cpu_init(0, S5P_VA_EXTGIC_CPU);
#else
	gic_cpu_base_addr = S5P_VA_GIC_CPU;
	gic_dist_init(0, S5P_VA_GIC_DIST, IRQ_SPI(0));
	gic_cpu_init(0, S5P_VA_GIC_CPU);
#endif

	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {

#ifdef CONFIG_CPU_S5PV310_EVT1
		/* From SPI(0) to SPI(39) and SPI(51), SPI(53)
		* are connected to the interrupt combiner. These irqs
		* should be initialized to support cascade interrupt.
		*/
		if ((irq >= 40) && !(irq == 51) && !(irq == 53))
			continue;
#endif

#ifdef CONFIG_USE_EXT_GIC
		combiner_init(irq, (void __iomem *)S5P_VA_EXTCOMBINER(irq),
				COMBINER_IRQ(irq, 0));
#else
		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
				COMBINER_IRQ(irq, 0));
#endif
		combiner_cascade_irq(irq, IRQ_SPI(irq));
	}

	/* The parameters of s5p_init_irq() are for VIC init.
	 * Theses parameters should be NULL and 0 because S5PV310
	 * uses GIC instead of VIC.
	 */
	s5p_init_irq(NULL, 0);

	/* Set s3c_irq_wake as set_wake() of GIC irq_chip */
	get_irq_chip(IRQ_RTC_ALARM)->set_wake = s3c_irq_wake;
}
Exemplo n.º 6
0
int __init combiner_of_init(struct device_node *np, struct device_node *parent)
{
    void __iomem *combiner_base;

    combiner_base = of_iomap(np, 0);
    if (!combiner_base) {
        pr_err("%s: failed to map combiner registers\n", __func__);
        return -ENXIO;
    }

    combiner_init(combiner_base, np);

    return 0;
}
Exemplo n.º 7
0
void __init exynos4_init_irq(void)
{
	unsigned int gic_bank_offset;

	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;

	if (!of_have_populated_dt())
		gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
#ifdef CONFIG_OF
	else
		of_irq_init(exynos_dt_irq_match);
#endif

	if (!of_have_populated_dt()) {
		combiner_init(S5P_VA_COMBINER_BASE, NULL);
		exynos_init_irq_eint(NULL, NULL);
	}
}
void __init s5pv310_init_irq(void)
{
	int irq;

	gic_cpu_base_addr = S5P_VA_GIC_CPU;
	gic_dist_init(0, S5P_VA_GIC_DIST, IRQ_LOCALTIMER);
	gic_cpu_init(0, S5P_VA_GIC_CPU);

	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
				COMBINER_IRQ(irq, 0));
		combiner_cascade_irq(irq, IRQ_SPI(irq));
	}

	/* The parameters of s5p_init_irq() are for VIC init.
	 * Theses parameters should be NULL and 0 because S5PV310
	 * uses GIC instead of VIC.
	 */
	s5p_init_irq(NULL, 0);
}
Exemplo n.º 9
0
static int __init combiner_of_init(struct device_node *np,
				   struct device_node *parent)
{
	void __iomem *combiner_base;
	unsigned int max_nr = 20;

	combiner_base = of_iomap(np, 0);
	if (!combiner_base) {
		pr_err("%s: failed to map combiner registers\n", __func__);
		return -ENXIO;
	}

	if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
		pr_info("%s: number of combiners not specified, "
			"setting default as %d.\n",
			__func__, max_nr);
	}

	combiner_init(combiner_base, np, max_nr);

	return 0;
}
Exemplo n.º 10
0
void __init exynos4_init_irq(void)
{
    unsigned int gic_bank_offset;

    gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;

    if (!of_have_populated_dt())
        gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
#ifdef CONFIG_OF
    else
        of_irq_init(exynos4_dt_irq_match);
#endif

    if (!of_have_populated_dt())
        combiner_init(S5P_VA_COMBINER_BASE, NULL);

    /*
     * The parameters of s5p_init_irq() are for VIC init.
     * Theses parameters should be NULL and 0 because EXYNOS4
     * uses GIC instead of VIC.
     */
    s5p_init_irq(NULL, 0);
}