static void commit_alu_instruction(struct schedule_state * s, struct schedule_instruction * sinst)
{
DBG("%i: commit\n", sinst->Instruction->IP);
commit_update_reads(s, sinst);
commit_update_writes(s, sinst);
}
static void commit_alu_instruction(struct schedule_state * s, struct schedule_instruction * sinst)
{
DBG("%i: commit score = %d\n", sinst->Instruction->IP, sinst->Score);
commit_update_reads(s, sinst);
commit_update_writes(s, sinst);
if (get_tex_read_count(sinst) > 0) {
sinst->Instruction->U.P.SemWait = 1;
notify_sem_wait(s);
}
}
/**
* Emit all ready texture instructions in a single block.
*
* Emit as a single block to (hopefully) sample many textures in parallel,
* and to avoid hardware indirections on R300.
*/
static void emit_all_tex(struct schedule_state * s, struct rc_instruction * before)
{
struct schedule_instruction *readytex;
struct rc_instruction * inst_begin;
assert(s->ReadyTEX);
notify_sem_wait(s);
/* Node marker for R300 */
inst_begin = rc_insert_new_instruction(s->C, before->Prev);
inst_begin->U.I.Opcode = RC_OPCODE_BEGIN_TEX;
/* Link texture instructions back in */
readytex = s->ReadyTEX;
while(readytex) {
rc_insert_instruction(before->Prev, readytex->Instruction);
DBG("%i: commit TEX reads\n", readytex->Instruction->IP);
/* All of the TEX instructions in the same TEX block have
* their source registers read from before any of the
* instructions in that block write to their destination
* registers. This means that when we commit a TEX
* instruction, any other TEX instruction that wants to write
* to one of the committed instruction's source register can be
* marked as ready and should be emitted in the same TEX
* block. This prevents the following sequence from being
* emitted in two different TEX blocks:
* 0: TEX temp[0].xyz, temp[1].xy__, 2D[0];
* 1: TEX temp[1].xyz, temp[2].xy__, 2D[0];
*/
commit_update_reads(s, readytex);
readytex = readytex->NextReady;
}
readytex = s->ReadyTEX;
s->ReadyTEX = 0;
while(readytex){
DBG("%i: commit TEX writes\n", readytex->Instruction->IP);
commit_update_writes(s, readytex);
/* Set semaphore bits for last TEX instruction in the block */
if (!readytex->NextReady) {
readytex->Instruction->U.I.TexSemAcquire = 1;
readytex->Instruction->U.I.TexSemWait = 1;
}
rc_list_add(&s->PendingTEX, rc_list(&s->C->Pool, readytex));
readytex = readytex->NextReady;
}
}
/**
* This function decreases the dependencies of the next instruction that
* wants to write to each of sinst's read values.
*/
static void commit_update_reads(struct schedule_state * s,
struct schedule_instruction * sinst){
unsigned int i;
for(i = 0; i < sinst->NumReadValues; ++i) {
struct reg_value * v = sinst->ReadValues[i];
assert(v->NumReaders > 0);
v->NumReaders--;
if (!v->NumReaders) {
if (v->Next) {
decrease_dependencies(s, v->Next->Writer);
}
}
}
if (sinst->PairedInst) {
commit_update_reads(s, sinst->PairedInst);
}
}