/******************************************************************************
* prcm_reinit_battery_chrg - inits only mpu_dpll clock as to reduce the core freq
* from 700Mhz to 350Mhz or 350Mhz to 700Mhz
*****************************************************************************/
void prcm_reinit_battery_chrg(u32 chrg_state)
{
u32 clk_index;
/* Get the sysclk speed from cm_sys_clksel */
clk_index = readl(CM_SYS_CLKSEL);
if ((!clk_index)&&(0x07 == clk_index) )
{
printf("Error: clk_index is wrong in uboot %d\n",clk_index);
return; /* Sys clk uninitialized */
}
if(0x01 == chrg_state )
{
configure_mpu_dpll(clk_index);
configure_iva_dpll(clk_index);
configure_core_dpll(clk_index);
configure_per_dpll(clk_index);
configure_abe_dpll(clk_index);
configure_usb_dpll(clk_index);
}
else
{
configure_mpu_dpll(clk_index + 1);
configure_iva_dpll(clk_index + 1);
configure_core_dpll(clk_index + 1);
configure_per_dpll(clk_index + 1);
configure_abe_dpll(clk_index + 1);
configure_usb_dpll(clk_index + 1);
}
}
static void setup_dplls(void)
{
u32 sysclk_ind, temp;
const struct dpll_params *params;
debug("setup_dplls\n");
sysclk_ind = get_sys_clk_index();
/* CORE dpll */
params = get_core_dpll_params(); /* default - safest */
/*
* Do not lock the core DPLL now. Just set it up.
* Core DPLL will be locked after setting up EMIF
* using the FREQ_UPDATE method(freq_update_core())
*/
do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK);
/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
(CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
(CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
writel(temp, &prcm->cm_clksel_core);
debug("Core DPLL configured\n");
/* lock PER dpll */
do_setup_dpll(&prcm->cm_clkmode_dpll_per,
&per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK);
debug("PER DPLL locked\n");
/* MPU dpll */
configure_mpu_dpll();
}
/******************************************************************************
* prcm_init() - inits clocks for PRCM as defined in clocks.h
* -- called from SRAM, or Flash (using temp SRAM stack).
*****************************************************************************/
void prcm_init(void)
{
u32 clk_index;
/* Get the sysclk speed from cm_sys_clksel
* Set the CM_SYS_CLKSEL in case ROM code has not set
*/
__raw_writel(0x7, CM_SYS_CLKSEL);
clk_index = readl(CM_SYS_CLKSEL);
if (!clk_index)
return; /* Sys clk uninitialized */
/* Core DPLL is locked using FREQ update method */
/* configure_core_dpll(clk_index - 1); */
/* Configure all DPLL's at 100% OPP */
configure_mpu_dpll(clk_index - 1);
configure_iva_dpll(clk_index - 1);
configure_per_dpll(clk_index - 1);
configure_abe_dpll(clk_index - 1);
configure_usb_dpll(clk_index - 1);
#ifdef CONFIG_OMAP4_SDC
/* Enable all clocks */
enable_all_clocks();
#endif
}
void uboot_prcm_high()
{
writel(7, CM_SYS_CLKSEL);
//configure_core_dpll(6);
configure_mpu_dpll(6);
// configure_iva_dpll(6);
// configure_per_dpll(6);
// configure_abe_dpll(6);
// configure_usb_dpll(6);
}
void set_mpu_dpll_max_opp(void)
{
u32 clk_index;
/* Get the sysclk speed from cm_sys_clksel */
/* We are only interested in the lowest 3 bits */
clk_index = readl(CM_SYS_CLKSEL) & 0x7;
if(!clk_index) return; /* Sys clk uninitialized */
/* Configure all DPLL's at 100% OPP */
configure_mpu_dpll(clk_index - 1);
}
static void setup_dplls(void)
{
u32 temp;
const struct dpll_params *params;
struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
debug("setup_dplls\n");
/* CORE dpll */
params = get_core_dpll_params(*dplls_data); /* default - safest */
/*
* Do not lock the core DPLL now. Just set it up.
* Core DPLL will be locked after setting up EMIF
* using the FREQ_UPDATE method(freq_update_core())
*/
if (emif_sdram_type(readl(&emif->emif_sdram_config)) ==
EMIF_SDRAM_TYPE_LPDDR2)
do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
DPLL_NO_LOCK, "core");
else
do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
DPLL_LOCK, "core");
/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
(CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
(CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
writel(temp, (*prcm)->cm_clksel_core);
debug("Core DPLL configured\n");
/* lock PER dpll */
params = get_per_dpll_params(*dplls_data);
do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
params, DPLL_LOCK, "per");
debug("PER DPLL locked\n");
/* MPU dpll */
configure_mpu_dpll();
#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
defined(CONFIG_USB_MUSB_OMAP2PLUS)
setup_usb_dpll();
#endif
params = get_ddr_dpll_params(*dplls_data);
do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
params, DPLL_LOCK, "ddr");
#ifdef CONFIG_DRIVER_TI_CPSW
params = get_gmac_dpll_params(*dplls_data);
do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
DPLL_LOCK, "gmac");
#endif
}
/* must be called from sram or flash */
void prcm_init(void)
{
u32 clk_index;
/* Get the sysclk speed from cm_sys_clksel
* Set the CM_SYS_CLKSEL in case ROM code has not set
*/
writel(0x7,CM_SYS_CLKSEL);
clk_index = readl(CM_SYS_CLKSEL);
if (!clk_index)
return;
/* Configure all DPLL's at 100% OPP */
configure_mpu_dpll(&mpu_dpll_param);
configure_iva_dpll(&iva_dpll_param);
configure_per_dpll(&per_dpll_param);
configure_abe_dpll(&abe_dpll_param);
configure_usb_dpll(&usb_dpll_param);
enable_all_clocks();
}
