static void twl4030_phy_resume(struct twl4030_usb *twl)
{
if (!twl->asleep)
return;
wake_lock(&twl->wake_lock);
#if defined(USB_LAT_CONST) && defined(CONFIG_OMAP3_PM)
/* Acquire USB constraint on OFF/RET */
if (twl->usb_power_constraint)
constraint_set(twl->usb_power_constraint,
CO_LATENCY_MPUOFF_COREON);
#endif
twl4030_phy_power(twl, 1);
twl4030_i2c_access(twl, 1);
twl4030_usb_set_mode(twl, twl->usb_mode);
if (twl->usb_mode == T2_USB_MODE_ULPI)
twl4030_i2c_access(twl, 0);
twl->asleep = 0;
#ifdef CONFIG_OMAP34XX_OFFMODE
/* Restore context of MUSB from OFF mode */
if (t2_transceiver->link_context_restore_and_wakeup)
t2_transceiver->link_context_restore_and_wakeup();
#endif
return;
}
static void _add_constraint(struct in_addr addr, int prefix_len, char *ip, int value)
{
constraint_set(constraint, ntohl(addr.s_addr), prefix_len, value);
const char *name;
if (value == ADDR_DISALLOWED)
name = "blacklisting";
else
name = "whitelisting";
log_trace(name, "%s %s/%i", name, ip, prefix_len);
}
static int init(char *file, const char *name, int value)
{
FILE *fp;
char line[1000];
fp = fopen(file, "r");
if (fp == NULL) {
log_fatal(name, "Unable to open %s file: %s: %s", name, file, strerror(errno));
}
while (fgets(line, sizeof(line), fp) != NULL) {
char *comment = strchr(line, '#');
if (comment) {
*comment = '\0';
}
char ip[33];
if ((sscanf(line, "%32s", ip)) == EOF) {
continue;
}
int prefix_len = 32;
char *slash = strchr(ip, '/');
if (slash) { // split apart network and prefix length
*slash = '\0';
char *end;
char *len = slash+1;
errno = 0;
prefix_len = strtol(len, &end, 10);
if (end == len || errno != 0 || prefix_len < 0 || prefix_len > 32) {
log_fatal(name, "Unable to parse %s file: %s ('%s' is not a valid prefix length)", name, file, len);
}
}
struct in_addr addr;
if (inet_aton(ip, &addr) == 0) {
log_fatal(name, "Unable to parse %s file: %s ('%s' is not a valid IP address)", name, file, ip);
}
constraint_set(constraint, ntohl(addr.s_addr), prefix_len, value);
log_trace(name, "%sing %s/%i",
name, ip, prefix_len);
}
fclose(fp);
return 0;
}
// whitelist a CIDR network allocation
void whitelist_prefix(char *ip, int prefix_len)
{
assert(constraint);
constraint_set(constraint, ntohl(inet_addr(ip)), prefix_len, ADDR_ALLOWED);
}
DSP_STATUS CHNLSM_InterruptDSP2(struct WMD_DEV_CONTEXT *pDevContext,
u16 wMbVal)
{
#ifndef CONFIG_DISABLE_BRIDGE_PM
#ifndef CONFIG_DISABLE_BRIDGE_DVFS
u32 opplevel;
#endif
#endif
struct CFG_HOSTRES resources;
unsigned long timeout;
u32 temp;
DSP_STATUS status = DSP_SOK;
/* We are waiting indefinitely here. This needs to be fixed in the
* second phase */
CFG_GetHostResources((struct CFG_DEVNODE *)DRV_GetFirstDevExtension(),
&resources);
if (pDevContext->dwBrdState == BRD_DSP_HIBERNATION ||
pDevContext->dwBrdState == BRD_HIBERNATION) {
#ifndef CONFIG_DISABLE_BRIDGE_PM
#ifndef CONFIG_DISABLE_BRIDGE_DVFS
#ifndef CONFIG_OMAP3_PM
opplevel = omap_pm_dsp_get_opp();
/* If OPP is at minimum level, increase it before waking up
* the DSP */
if (opplevel == 1) {
omap_pm_dsp_set_min_opp(opplevel+1);
DBG_Trace(DBG_LEVEL7, "CHNLSM_InterruptDSP:Setting "
"the vdd1 constraint level to %d before "
"waking DSP \n", (opplevel + 1));
}
#else
opplevel = constraint_get_level(dsp_constraint_handle);
/* If OPP is at minimum level, increase it before waking up
* the DSP */
if (opplevel == 1) {
if (constraint_set(dsp_constraint_handle,
(opplevel+1)) != 0) {
DBG_Trace(DBG_LEVEL7, "CHNLSM_InterruptDSP: "
"Constraint set failed\n");
return DSP_EFAIL;
}
DBG_Trace(DBG_LEVEL7, "CHNLSM_InterruptDSP:Setting "
"the vdd1 constraint level to %d before "
"waking DSP \n", (opplevel + 1));
}
#endif
#endif
#endif
/* Restart the IVA clock that was disabled while
* the DSP initiated Hibernation. */
if ((pDevContext->dwBrdState == BRD_DSP_HIBERNATION)
|| (pDevContext->dwBrdState == BRD_HIBERNATION)) {
status = CLK_Enable(SERVICESCLK_iva2_ck);
if (DSP_FAILED(status))
return status;
}
/* Read MMU register to invoke short wakeup of DSP */
temp = (u32) *((REG_UWORD32 *) ((u32)
(resources.dwDmmuBase) + 0x10));
/* Restore mailbox settings */
HW_MBOX_restoreSettings(resources.dwMboxBase);
DBG_Trace(DBG_LEVEL6, "MailBoxSettings: SYSCONFIG = 0x%x\n",
mboxsetting.sysconfig);
DBG_Trace(DBG_LEVEL6, "MailBoxSettings: IRQENABLE0 = 0x%x\n",
mboxsetting.irqEnable0);
DBG_Trace(DBG_LEVEL6, "MailBoxSettings: IRQENABLE1 = 0x%x\n",
mboxsetting.irqEnable1);
/* Restart the peripheral clocks that were disabled only
* in DSP initiated Hibernation case.*/
if (pDevContext->dwBrdState == BRD_DSP_HIBERNATION)
DSP_PeripheralClocks_Enable(pDevContext, NULL);
pDevContext->dwBrdState = BRD_RUNNING;
}
timeout = jiffies + msecs_to_jiffies(35);
while (HW_MBOX_IsFull(resources.dwMboxBase, MBOX_ARM2DSP)) {
if (time_after(jiffies, timeout)) {
printk(KERN_ERR "dspbridge: "
"timed out waiting for mailbox\n");
return WMD_E_TIMEOUT;
}
}
DBG_Trace(DBG_LEVEL3, "writing %x to Mailbox\n",
wMbVal);
HW_MBOX_MsgWrite(resources.dwMboxBase, MBOX_ARM2DSP,
wMbVal);
return DSP_SOK;
}
PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
struct clk *psCLK;
IMG_INT res;
PVRSRV_ERROR eError;
IMG_BOOL bPowerLock;
#if defined(DEBUG) || defined(TIMING)
IMG_INT rate;
struct clk *sys_ck;
IMG_CPU_PHYADDR TimerRegPhysBase;
IMG_HANDLE hTimerEnable;
IMG_UINT32 *pui32TimerEnable;
#endif
PVR_TRACE(("EnableSystemClocks: Enabling System Clocks"));
if (!psSysSpecData->bSysClocksOneTimeInit)
{
bPowerLock = IMG_FALSE;
spin_lock_init(&psSysSpecData->sPowerLock);
atomic_set(&psSysSpecData->sPowerLockCPU, -1);
spin_lock_init(&psSysSpecData->sNotifyLock);
atomic_set(&psSysSpecData->sNotifyLockCPU, -1);
atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
psCLK = clk_get(NULL, "sgx_ck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSsystemClocks: Couldn't get SGX Functional Clock"));
goto ExitError;
}
psSysSpecData->psSGX_FCK = psCLK;
psSysSpecData->bSysClocksOneTimeInit = IMG_TRUE;
}
else
{
bPowerLock = PowerLockWrappedOnCPU(psSysSpecData);
if (bPowerLock)
{
PowerLockUnwrap(psSysSpecData);
}
}
#if defined(CONSTRAINT_NOTIFICATIONS)
psSysSpecData->pVdd2Handle = constraint_get(PVRSRV_MODNAME, &cnstr_id_vdd2);
if (IS_ERR(psSysSpecData->pVdd2Handle))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get VDD2 constraint handle"));
goto ExitError;
}
RegisterConstraintNotifications();
#endif
#if defined(DEBUG) || defined(TIMING)
if(cpu_is_ti816x()) {
psCLK = clk_get(NULL, "gpt6_fck");
} else {
psCLK = clk_get(NULL, "gpt7_fck");
}
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock"));
goto ExitUnRegisterConstraintNotifications;
}
psSysSpecData->psGPT11_FCK = psCLK;
if(cpu_is_ti816x()) {
psCLK = clk_get(NULL, "gpt6_ick");
} else {
psCLK = clk_get(NULL, "gpt7_ick");
}
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock"));
goto ExitUnRegisterConstraintNotifications;
}
psSysSpecData->psGPT11_ICK = psCLK;
rate = clk_get_rate(psSysSpecData->psGPT11_FCK);
PVR_TRACE(("GPTIMER11 clock is %dMHz", HZ_TO_MHZ(rate)));
res = clk_enable(psSysSpecData->psGPT11_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res));
goto ExitUnRegisterConstraintNotifications;
}
res = clk_enable(psSysSpecData->psGPT11_ICK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 interface clock (%d)", res));
goto ExitDisableGPT11FCK;
}
TimerRegPhysBase.uiAddr = SYS_TI81xx_GP7TIMER_TSICR_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
rate = *pui32TimerEnable;
if(!(rate & 4))
{
PVR_TRACE(("Setting GPTIMER11 mode to posted (currently is non-posted)"));
*pui32TimerEnable = rate | 4;
}
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
TimerRegPhysBase.uiAddr = SYS_TI81xx_GP7TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
*pui32TimerEnable = 3;
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
#endif
#if defined(PDUMP) && !defined(NO_HARDWARE) && defined(CONSTRAINT_NOTIFICATIONS)
PVR_TRACE(("EnableSystemClocks: Setting SGX OPP constraint"));
res = constraint_set(psSysSpecData->pVdd2Handle, max_vdd2_opp);
if (res != 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: constraint_set failed (%d)", res));
goto ExitConstraintSetFailed;
}
#endif
eError = PVRSRV_OK;
goto Exit;
#if defined(PDUMP) && !defined(NO_HARDWARE) && defined(CONSTRAINT_NOTIFICATIONS)
ExitConstraintSetFailed:
#endif
#if defined(DEBUG) || defined(TIMING)
ExitDisableGPT11ICK:
clk_disable(psSysSpecData->psGPT11_ICK);
ExitDisableGPT11FCK:
clk_disable(psSysSpecData->psGPT11_FCK);
ExitUnRegisterConstraintNotifications:
#endif
#if defined(CONSTRAINT_NOTIFICATIONS)
UnRegisterConstraintNotifications();
constraint_put(psSysSpecData->pVdd2Handle);
#endif
Exit:
if (bPowerLock)
{
PowerLockWrap(psSysSpecData);
}
ExitError:
eError = PVRSRV_ERROR_DISABLE_CLOCK_FAILURE;
return eError;
}
