DB_SHOW_COMMAND(cp15, db_show_cp15)
{
u_int reg;
reg = cp15_midr_get();
db_printf("Cpu ID: 0x%08x\n", reg);
reg = cp15_ctr_get();
db_printf("Current Cache Lvl ID: 0x%08x\n",reg);
reg = cp15_sctlr_get();
db_printf("Ctrl: 0x%08x\n",reg);
reg = cp15_actlr_get();
db_printf("Aux Ctrl: 0x%08x\n",reg);
reg = cp15_id_pfr0_get();
db_printf("Processor Feat 0: 0x%08x\n", reg);
reg = cp15_id_pfr1_get();
db_printf("Processor Feat 1: 0x%08x\n", reg);
reg = cp15_id_dfr0_get();
db_printf("Debug Feat 0: 0x%08x\n", reg);
reg = cp15_id_afr0_get();
db_printf("Auxiliary Feat 0: 0x%08x\n", reg);
reg = cp15_id_mmfr0_get();
db_printf("Memory Model Feat 0: 0x%08x\n", reg);
reg = cp15_id_mmfr1_get();
db_printf("Memory Model Feat 1: 0x%08x\n", reg);
reg = cp15_id_mmfr2_get();
db_printf("Memory Model Feat 2: 0x%08x\n", reg);
reg = cp15_id_mmfr3_get();
db_printf("Memory Model Feat 3: 0x%08x\n", reg);
reg = cp15_ttbr_get();
db_printf("TTB0: 0x%08x\n", reg);
}
/* Read and parse CPU id scheme */
void
cpuinfo_init(void)
{
cpuinfo.midr = cp15_midr_get();
/* Test old version id schemes first */
if ((cpuinfo.midr & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD) {
if (CPU_ID_ISOLD(cpuinfo.midr)) {
/* obsolete ARMv2 or ARMv3 CPU */
cpuinfo.midr = 0;
return;
}
if (CPU_ID_IS7(cpuinfo.midr)) {
if ((cpuinfo.midr & (1 << 23)) == 0) {
/* obsolete ARMv3 CPU */
cpuinfo.midr = 0;
return;
}
/* ARMv4T CPU */
cpuinfo.architecture = 1;
cpuinfo.revision = (cpuinfo.midr >> 16) & 0x7F;
} else {
/* ARM new id scheme */
cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F;
cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F;
}
} else {
