Exemplo n.º 1
0
PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
{
	SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
	int err;

	PVR_TRACE(("EnableSystemClocks: Enabling System Clocks"));

	/* power up */
	err = cpm_pwc_enable(psSysSpecData->pCPMHandle);
	if (err) {
		PVR_DPF((PVR_DBG_ERROR, "%s failed to power up GPU: %d", __func__, err));
		return PVRSRV_ERROR_UNKNOWN_POWER_STATE;
	}

	/* enable clock */
	err = clk_set_rate(psSysSpecData->psSGXClock, SYS_SGX_CLOCK_SPEED);
	if (!err)
		err = clk_prepare_enable(psSysSpecData->psSGXClock);
	if (err) {
		PVR_DPF((PVR_DBG_ERROR, "%s failed to initialise GPU clock: %d", __func__, err));
		return PVRSRV_ERROR_CLOCK_REQUEST_FAILED;
	}

	return PVRSRV_OK;
}
Exemplo n.º 2
0
void __init init_pwc_clk(struct clk *clk)
{
	struct clk *p;
	struct cpm_pwc *pwc;
	unsigned int id;

	id = CLK_PWC_NO(clk->flags);
	pwc = &cpm_pwc_srcs[CLK_PWC_NO(clk->flags)];
	clk->rate = 0;
	pwc->name = clk->name;
	clk->ops = &clk_pwc_ops;
	if (clk->flags & CLK_FLG_RELATIVE) {
		id = CLK_RELATIVE(clk->flags);
		p = get_clk_from_id(id);
		p->child = clk;
		clk->parent = clk;
		if(p->flags & CLK_FLG_ENABLE)
			cpm_pwc_enable(clk,1);
		else
			cpm_pwc_enable(clk,0);

	}
	clk->parent = NULL;
}
Exemplo n.º 3
0
static int vpu_on(struct jz_vpu *vpu)
{
	if (cpm_inl(CPM_OPCR) & OPCR_IDLE)
		return -EBUSY;

	clk_enable(vpu->clk);
	clk_enable(vpu->clk_gate);
	cpm_pwc_enable(vpu->cpm_pwc);

	__asm__ __volatile__ (
			"mfc0  $2, $16,  7   \n\t"
			"ori   $2, $2, 0x340 \n\t"
			"andi  $2, $2, 0x3ff \n\t"
			"mtc0  $2, $16,  7  \n\t"
			"nop                  \n\t");
	enable_irq(vpu->irq);
	//wake_lock(&vpu->wake_lock);
	dev_dbg(vpu->dev, "[%d:%d] on\n", current->tgid, current->pid);

	return 0;
}
Exemplo n.º 4
0
static void __cpuinit jzsoc_boot_secondary(int cpu, struct task_struct *idle)
{
	int err;
	unsigned long flags,ctrl;


	printk("jzsoc_boot_secondary start\n");
	local_irq_save(flags);

	/* set reset bit! */
	ctrl = get_smp_ctrl();
	ctrl |= (1 << cpu);
	set_smp_ctrl(ctrl);

	/* blast all cache before booting secondary cpu */
	blast_dcache_jz();
	blast_icache_jz();

	cpm_clear_bit(15,CPM_CLKGR1);
	cpm_pwc_enable(scpu_pwc);
	preempt_disable();
	preempt_enable_no_resched();

	/* clear reset bit! */
	ctrl = get_smp_ctrl();
	ctrl &= ~(1 << cpu);
	set_smp_ctrl(ctrl);
wait:
	if (!cpumask_test_cpu(cpu, cpu_ready))
		goto wait;
	pr_info("[SMP] Booting CPU%d ...\n", cpu);
//	pr_debug("[SMP] Booting CPU%d ...\n", cpu);
	err = cpu_boot(cpu_logical_map(cpu), __KSTK_TOS(idle),
			(unsigned long)task_thread_info(idle));
	if (err != 0)
		pr_err("start_cpu(%i) returned %i\n" , cpu, err);
	local_irq_restore(flags);
}