/**
* cppi41_controller_stop - stop DMA controller
* @controller: the controller
*
* De-initialize the DMA Controller as necessary.
*/
static int cppi41_controller_stop(struct dma_controller *controller)
{
struct cppi41 *cppi;
void __iomem *reg_base;
cppi = container_of(controller, struct cppi41, controller);
/*
* pop all the teardwon descriptor queued to tdQueue
*/
cppi41_free_teardown_queue(0);
/* Free the teardown completion queue */
if (cppi41_queue_free(usb_cppi41_info.q_mgr, cppi->teardownQNum))
DBG(1, "ERROR: failed to free teardown completion queue\n");
/*
* Free the packet descriptor region allocated
* for all Tx/Rx channels.
*/
if (cppi41_mem_rgn_free(usb_cppi41_info.q_mgr, cppi->pd_mem_rgn))
DBG(1, "ERROR: failed to free queue manager memory region\n");
dma_free_coherent(cppi->musb->controller,
USB_CPPI41_MAX_PD * USB_CPPI41_DESC_ALIGN,
cppi->pd_mem, cppi->pd_mem_phys);
reg_base = cppi->musb->ctrl_base;
/* Disable auto request mode */
musb_writel(reg_base, USB_AUTOREQ_REG, 0);
/* Disable the CDC/RNDIS modes */
musb_writel(reg_base, USB_TX_MODE_REG, 0);
musb_writel(reg_base, USB_RX_MODE_REG, 0);
return 1;
}
int cppi41_dma_block_uninit(u8 dma_num, u8 q_mgr, u8 num_order,
u32 *sched_tbl, u8 tbl_size)
{
const struct cppi41_dma_block *dma_block;
unsigned num_reg;
int i;
/* popout all teardown descriptors */
cppi41_free_teardown_queue(dma_num);
/* free queue mgr region */
cppi41_mem_rgn_free(q_mgr, dma_teardown[dma_num].mem_rgn);
/* free the allocated teardown descriptors */
dma_free_coherent(NULL, dma_teardown[dma_num].rgn_size,
dma_teardown[dma_num].virt_addr,
dma_teardown[dma_num].phys_addr);
/* free the teardown queue*/
cppi41_queue_free(dma_teardown[dma_num].q_mgr,
dma_teardown[dma_num].q_num);
dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
/* disable the dma schedular */
num_reg = (tbl_size + 3) / 4;
for (i = 0; i < num_reg; i++) {
cppi_writel(0, dma_block->sched_table_base +
DMA_SCHED_TABLE_WORD_REG(i));
DBG("DMA scheduler table @ %p, value written: %x\n",
dma_block->sched_table_base + DMA_SCHED_TABLE_WORD_REG(i),
0);
}
cppi_writel(0, dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG);
return 0;
}
