bool checkForLpcBug( void )
{
// See HW400314 for description of hardware bug
// The Power Bus Snooper Interface on the ADU is shared by both PIB
// and LPC. Once an error occurred in the Xscom while accessing the
// PIB space, the interface is overriding the data that is sent out
// as all ?F? for any operation which may be XSCOM to PIB address
// space or to a LPC address Space. Further XSCOM operation are
// locked till the pending error is cleared. But an XSCOM Status
// pmisc is sent with pib response info (in this case the type of
// the error) and for the next operations i.e. XSCOM to PIB or to
// LPC it sends info value as 1 which indicates ADU has pending
// XSCOM Error. This is indicated in the (48 :50) bits in the address
// sent.
ProcessorCoreType l_coreType = cpu_core_type();
uint8_t l_ddLevel = cpu_dd_level();
// Bug is only present in Nimbus DD1
if( (l_coreType == CORE_POWER9_NIMBUS) && (l_ddLevel == 0x10) )
{
TRACFCOMP( g_trac_xscom, "Activating LPC mutex workaround" );
return true;
}
else
{
return false;
}
}
/**
* @brief Check that at least one processor of our cpu type is being targeted
*/
static void checkProcessorTargeting(TargetService& i_targetService)
{
#define TARG_FN "checkProcessorTargeting()"
TARG_ENTER();
PredicateCTM l_procChip(CLASS_CHIP,TYPE_PROC);
ProcessorCoreType l_coreType = cpu_core_type();
bool l_haveOneCorrectProcessor = false;
TargetRangeFilter l_filter(
i_targetService.begin(),
i_targetService.end(),
&l_procChip);
for(;l_filter && (l_haveOneCorrectProcessor != true);++l_filter)
{
switch(l_filter->getAttr<ATTR_MODEL>())
{
case MODEL_VENICE:
if(l_coreType == CORE_POWER8_VENICE)
{
l_haveOneCorrectProcessor = true;
}
break;
case MODEL_MURANO:
if(l_coreType == CORE_POWER8_MURANO)
{
l_haveOneCorrectProcessor = true;
}
break;
case MODEL_NAPLES:
if(l_coreType == CORE_POWER8_NAPLES)
{
l_haveOneCorrectProcessor = true;
}
break;
default:
break;
};
}
TARG_ASSERT((l_haveOneCorrectProcessor == true), TARG_ERR_LOC "FATAL: No "
"targeted processors are of the correct type");
TARG_EXIT();
#undef TARG_FN
}
/**
* @brief Returns maximum processors chip per node
* base on system type
*
* @return uint8_t
*/
uint8_t getMaxChipsPerNode()
{
uint8_t l_numOfChips = 0;
ProcessorCoreType l_coreType = cpu_core_type();
switch (l_coreType)
{
case CORE_POWER8_MURANO:
case CORE_POWER8_VENICE:
case CORE_POWER8_NAPLES:
case CORE_UNKNOWN:
default:
l_numOfChips = 8;
break;
}
return l_numOfChips;
}
