static void ori_to_ccr(struct cpu *cpu, WORD op) { WORD d; ENTER; ADD_CYCLE(20); d = bus_read_word(cpu->pc)&0x1f; cpu->pc += 2; cpu_set_sr(cpu->sr|d); cpu_prefetch(); }
static void andi_to_sr(struct cpu *cpu, WORD op) { WORD d; ENTER; if(cpu->sr&0x2000) { ADD_CYCLE(20); d = bus_read_word(cpu->pc); cpu->pc += 2; cpu_set_sr(cpu->sr&d); cpu->tracedelay = 1; } else { cpu_set_exception(8); /* Privilege violation */ } }
int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUClass *cc = CPU_GET_CLASS(cs); CPUOpenRISCState *env = &cpu->env; uint32_t tmp; if (n > cc->gdb_num_core_regs) { return 0; } tmp = ldl_p(mem_buf); if (n < 32) { env->gpr[n] = tmp; } else { switch (n) { case 32: /* PPC */ env->ppc = tmp; break; case 33: /* NPC (equals PC) */ /* If setting PC to something different, also clear delayed branch status. */ if (env->pc != tmp) { env->pc = tmp; env->dflag = 0; } break; case 34: /* SR */ cpu_set_sr(env, tmp); break; default: break; } } return 4; }
static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { CPUOpenRISCState *env = opaque; cpu_set_sr(env, qemu_get_be32(f)); return 0; }