static WRITE8_HANDLER( mcu_tnzs_w )
{
// logerror("PC %04x: write %02x to mcu $c00%01x\n", activecpu_get_previouspc(), data, offset);
if (offset == 0)
cpunum_set_reg(2, I8X41_DATA, data);
else
cpunum_set_reg(2, I8X41_CMND, data);
}
static QUICKLOAD_LOAD( jaguar )
{
offs_t quickload_begin = 0x4000;
quickload_size = MIN(quickload_size, 0x200000 - quickload_begin);
mame_fread(fp, &memory_region(REGION_CPU1)[quickload_begin], quickload_size);
cpunum_set_reg(0, REG_PC, quickload_begin);
return INIT_PASS;
}
static void lviv_setup_snapshot (UINT8 * data)
{
unsigned char lo,hi;
/* Set registers */
lo = data[0x14112] & 0x0ff;
hi = data[0x14111] & 0x0ff;
cpunum_set_reg(0, I8080_BC, (hi << 8) | lo);
lo = data[0x14114] & 0x0ff;
hi = data[0x14113] & 0x0ff;
cpunum_set_reg(0, I8080_DE, (hi << 8) | lo);
lo = data[0x14116] & 0x0ff;
hi = data[0x14115] & 0x0ff;
cpunum_set_reg(0, I8080_HL, (hi << 8) | lo);
lo = data[0x14118] & 0x0ff;
hi = data[0x14117] & 0x0ff;
cpunum_set_reg(0, I8080_AF, (hi << 8) | lo);
lo = data[0x14119] & 0x0ff;
hi = data[0x1411a] & 0x0ff;
cpunum_set_reg(0, I8080_SP, (hi << 8) | lo);
lo = data[0x1411b] & 0x0ff;
hi = data[0x1411c] & 0x0ff;
cpunum_set_reg(0, I8080_PC, (hi << 8) | lo);
/* Memory dump */
memcpy (mess_ram, data+0x0011, 0xc000);
memcpy (mess_ram+0xc000, data+0x10011, 0x4000);
/* Ports */
lviv_ppi_port_outputs[0][0] = data[0x14011+0xc0];
lviv_ppi_port_outputs[0][1] = data[0x14011+0xc1];
lviv_update_palette (lviv_ppi_port_outputs[0][1]&0x7f);
lviv_ppi_port_outputs[0][2] = data[0x14011+0xc2];
lviv_update_memory();
}
static void c128_bankswitch (int reset)
{
if (mmu_cpu != MMU_CPU8502)
{
if (!MMU_CPU8502)
{
DBG_LOG (1, "switching to z80",
("active %d\n",cpu_getactivecpu()) );
memory_set_context(0);
c128_bankswitch_z80();
memory_set_context(1);
cpunum_set_input_line(0, INPUT_LINE_HALT, CLEAR_LINE);
cpunum_set_input_line(1, INPUT_LINE_HALT, ASSERT_LINE);
}
else
{
DBG_LOG (1, "switching to m6502",
("active %d\n",cpu_getactivecpu()) );
memory_set_context(1);
c128_bankswitch_128(reset);
memory_set_context(0);
cpunum_set_input_line(0, INPUT_LINE_HALT, ASSERT_LINE);
cpunum_set_input_line(1, INPUT_LINE_HALT, CLEAR_LINE);
/* NPW 19-Nov-2005 - In the C128, CPU #0 starts out and hands over
* control to CPU #1. CPU #1 seems to execute garbage from 0x0000
* up to 0x1100, at which point it finally hits some code
* (presumably set up by CPU #1.) This always worked, but when I
* changed the m8502 CPU core to use an internal memory map, it
* started BRK-ing forever when trying to execute 0x0000.
*
* I am not sure whether the C128 actually executes this invalid
* memory or if this is a bug in the C128 driver. In any case, the
* driver used to work with this behavior, so I am doing this hack
* where I set CPU #1's PC to 0x1100 on reset.
*/
if (cpunum_get_reg(1, REG_PC) == 0x0000)
cpunum_set_reg(1, REG_PC, 0x1100);
}
mmu_cpu = MMU_CPU8502;
return;
}
if (!MMU_CPU8502)
c128_bankswitch_z80();
else
c128_bankswitch_128(reset);
}
static void primo_setup_pp (UINT8* quickload_data, UINT32 quickload_size)
{
int i;
UINT16 load_addr;
UINT16 start_addr;
load_addr = quickload_data[0] + quickload_data[1]*256;
start_addr = quickload_data[2] + quickload_data[3]*256;
for (i=4; i<quickload_size; i++)
program_write_byte(start_addr+i-4, quickload_data[i]);
cpunum_set_reg(0, Z80_PC, start_addr);
logerror ("Quickload .pp l: %04x r: %04x s: %04x\n", load_addr, start_addr, quickload_size-4);
}
static void kc85_disk_reset_timer_callback(int dummy)
{
cpunum_set_reg(1, REG_PC, 0x0f000);
cpunum_set_reg(0, REG_PC, 0x0f000);
}
static void galaxy_setup_snapshot (const UINT8 * data, UINT32 size)
{
switch (size)
{
case GALAXY_SNAPSHOT_V1_SIZE:
cpunum_set_reg(0, Z80_AF, data[0x00] | data[0x01]<<8);
cpunum_set_reg(0, Z80_BC, data[0x04] | data[0x05]<<8);
cpunum_set_reg(0, Z80_DE, data[0x08] | data[0x09]<<8);
cpunum_set_reg(0, Z80_HL, data[0x0c] | data[0x0d]<<8);
cpunum_set_reg(0, Z80_IX, data[0x10] | data[0x11]<<8);
cpunum_set_reg(0, Z80_IY, data[0x14] | data[0x15]<<8);
cpunum_set_reg(0, Z80_PC, data[0x18] | data[0x19]<<8);
cpunum_set_reg(0, Z80_SP, data[0x1c] | data[0x1d]<<8);
cpunum_set_reg(0, Z80_AF2, data[0x20] | data[0x21]<<8);
cpunum_set_reg(0, Z80_BC2, data[0x24] | data[0x25]<<8);
cpunum_set_reg(0, Z80_DE2, data[0x28] | data[0x29]<<8);
cpunum_set_reg(0, Z80_HL2, data[0x2c] | data[0x2d]<<8);
cpunum_set_reg(0, Z80_IFF1, data[0x30]);
cpunum_set_reg(0, Z80_IFF2, data[0x34]);
cpunum_set_reg(0, Z80_HALT, data[0x38]);
cpunum_set_reg(0, Z80_IM, data[0x3c]);
cpunum_set_reg(0, Z80_I, data[0x40]);
cpunum_set_reg(0, Z80_R, (data[0x44]&0x7f) | (data[0x48]&0x80));
memcpy (mess_ram, data+0x084c, (mess_ram_size < 0x1800) ? mess_ram_size : 0x1800);
break;
case GALAXY_SNAPSHOT_V2_SIZE:
cpunum_set_reg(0, Z80_AF, data[0x00] | data[0x01]<<8);
cpunum_set_reg(0, Z80_BC, data[0x02] | data[0x03]<<8);
cpunum_set_reg(0, Z80_DE, data[0x04] | data[0x05]<<8);
cpunum_set_reg(0, Z80_HL, data[0x06] | data[0x07]<<8);
cpunum_set_reg(0, Z80_IX, data[0x08] | data[0x09]<<8);
cpunum_set_reg(0, Z80_IY, data[0x0a] | data[0x0b]<<8);
cpunum_set_reg(0, Z80_PC, data[0x0c] | data[0x0d]<<8);
cpunum_set_reg(0, Z80_SP, data[0x0e] | data[0x0f]<<8);
cpunum_set_reg(0, Z80_AF2, data[0x10] | data[0x11]<<8);
cpunum_set_reg(0, Z80_BC2, data[0x12] | data[0x13]<<8);
cpunum_set_reg(0, Z80_DE2, data[0x14] | data[0x15]<<8);
cpunum_set_reg(0, Z80_HL2, data[0x16] | data[0x17]<<8);
cpunum_set_reg(0, Z80_IFF1, data[0x18]&0x01);
cpunum_set_reg(0, Z80_IFF2, 0);
cpunum_set_reg(0, Z80_HALT, 0);
cpunum_set_reg(0, Z80_IM, (data[0x18]>>1)&0x03);
cpunum_set_reg(0, Z80_I, data[0x19]);
cpunum_set_reg(0, Z80_R, data[0x1a]);
memcpy (mess_ram, data+0x0834, (mess_ram_size < 0x1800) ? mess_ram_size : 0x1800);
break;
}
cpunum_set_input_line(0, INPUT_LINE_NMI, CLEAR_LINE);
cpunum_set_input_line(0, INPUT_LINE_IRQ0, CLEAR_LINE);
}
static void exidy_reset_timer_callback(int dummy)
{
cpunum_set_reg(0, REG_PC, 0x0e000);
}
static void primo_setup_pss (UINT8* snapshot_data, UINT32 snapshot_size)
{
int i;
/* Z80 registers */
cpunum_set_reg(0, Z80_BC, snapshot_data[4] + snapshot_data[5]*256);
cpunum_set_reg(0, Z80_DE, snapshot_data[6] + snapshot_data[7]*256);
cpunum_set_reg(0, Z80_HL, snapshot_data[8] + snapshot_data[9]*256);
cpunum_set_reg(0, Z80_AF, snapshot_data[10] + snapshot_data[11]*256);
cpunum_set_reg(0, Z80_BC2, snapshot_data[12] + snapshot_data[13]*256);
cpunum_set_reg(0, Z80_DE2, snapshot_data[14] + snapshot_data[15]*256);
cpunum_set_reg(0, Z80_HL2, snapshot_data[16] + snapshot_data[17]*256);
cpunum_set_reg(0, Z80_AF2, snapshot_data[18] + snapshot_data[19]*256);
cpunum_set_reg(0, Z80_PC, snapshot_data[20] + snapshot_data[21]*256);
cpunum_set_reg(0, Z80_SP, snapshot_data[22] + snapshot_data[23]*256);
cpunum_set_reg(0, Z80_I, snapshot_data[24]);
cpunum_set_reg(0, Z80_R, snapshot_data[25]);
cpunum_set_reg(0, Z80_IX, snapshot_data[26] + snapshot_data[27]*256);
cpunum_set_reg(0, Z80_IY, snapshot_data[28] + snapshot_data[29]*256);
/* IO ports */
// KI-1 bit 7 - NMI generator enable/disable
primo_nmi = (snapshot_data[30] & 0x80) ? 1 : 0;
// KI-1 bit 4 - speaker
speaker_level_w(0, (snapshot_data[30]&0x10)>>4);
/* memory */
for (i=0; i<0xc000; i++)
program_write_byte(i+0x4000, snapshot_data[i+38]);
}
