bool mgos_uart_hal_init(struct mgos_uart_state *us) {
uint32_t base = cc32xx_uart_get_base(us->uart_no);
uint32_t periph, int_no;
void (*int_handler)();
/* TODO(rojer): Configurable pin mappings? */
if (us->uart_no == 0) {
periph = PRCM_UARTA0;
int_no = INT_UARTA0;
int_handler = u0_int;
MAP_PinTypeUART(PIN_55, PIN_MODE_3); /* UART0_TX */
MAP_PinTypeUART(PIN_57, PIN_MODE_3); /* UART0_RX */
} else if (us->uart_no == 1) {
periph = PRCM_UARTA1;
int_no = INT_UARTA1;
int_handler = u1_int;
MAP_PinTypeUART(PIN_07, PIN_MODE_5); /* UART1_TX */
MAP_PinTypeUART(PIN_08, PIN_MODE_5); /* UART1_RX */
} else {
return false;
}
struct cc32xx_uart_state *ds =
(struct cc32xx_uart_state *) calloc(1, sizeof(*ds));
ds->base = base;
cs_rbuf_init(&ds->isr_rx_buf, CC32xx_UART_ISR_RX_BUF_SIZE);
us->dev_data = ds;
MAP_PRCMPeripheralClkEnable(periph, PRCM_RUN_MODE_CLK);
MAP_UARTIntDisable(base, ~0); /* Start with ints disabled. */
MAP_IntRegister(int_no, int_handler);
MAP_IntPrioritySet(int_no, INT_PRIORITY_LVL_1);
MAP_IntEnable(int_no);
return true;
}
int esp_uart_init(struct esp_uart_config *cfg) {
if (cfg == NULL || !esp_uart_validate_config(cfg)) return 0;
struct esp_uart_state *us = s_us[cfg->uart_no];
if (us != NULL) {
s_us[cfg->uart_no] = NULL;
esp_uart_deinit(us);
}
us = calloc(1, sizeof(*us));
us->cfg = cfg;
cs_rbuf_init(&us->rx_buf, cfg->rx_buf_size);
cs_rbuf_init(&us->tx_buf, cfg->tx_buf_size);
ETS_INTR_DISABLE(ETS_UART_INUM);
uart_div_modify(cfg->uart_no, UART_CLK_FREQ / cfg->baud_rate);
if (cfg->uart_no == 0) {
PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
if (cfg->swap_rxtx_ctsrts) {
SET_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
PERI_IO_UART0_PIN_SWAP);
} else {
CLEAR_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
PERI_IO_UART0_PIN_SWAP);
}
} else {
PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO2_U);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
if (cfg->swap_rxtx_ctsrts) {
SET_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
PERI_IO_UART1_PIN_SWAP);
} else {
CLEAR_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
PERI_IO_UART1_PIN_SWAP);
}
}
unsigned int conf0 = 0b011100; /* 8-N-1 */
if (cfg->tx_fc_ena) {
conf0 |= UART_TX_FLOW_EN;
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_U0CTS);
}
WRITE_PERI_REG(UART_CONF0(cfg->uart_no), conf0);
unsigned int conf1 = cfg->rx_fifo_full_thresh;
conf1 |= (cfg->tx_fifo_empty_thresh << 8);
if (cfg->rx_fifo_alarm >= 0) {
conf1 |= UART_RX_TOUT_EN | ((cfg->rx_fifo_alarm & 0x7f) << 24);
}
if (cfg->rx_fc_ena && cfg->rx_fifo_fc_thresh > 0) {
/* UART_RX_FLOW_EN will be set in uart_start. */
conf1 |= ((cfg->rx_fifo_fc_thresh & 0x7f) << 16);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS);
}
WRITE_PERI_REG(UART_CONF1(cfg->uart_no), conf1);
if (cfg->status_interval_ms > 0) {
os_timer_disarm(&us->status_timer);
os_timer_setfn(&us->status_timer, esp_uart_print_status, us);
os_timer_arm(&us->status_timer, cfg->status_interval_ms, 1 /* repeat */);
}
s_us[cfg->uart_no] = us;
/* Start with TX and RX ints disabled. */
WRITE_PERI_REG(UART_INT_ENA(cfg->uart_no), UART_INFO_INTS);
ETS_UART_INTR_ATTACH(esp_uart_isr, NULL);
ETS_INTR_ENABLE(ETS_UART_INUM);
return 1;
}
