/*
* Set-up the external crystal oscillator, PLL1, CPU core clock and
* all necessary clocks for peripherals.
*/
static void clock_setup(void)
{
int lock_count = 0;
/*
* Configure and enable the external crystal oscillator
* (make sure it's turned off while setting its mode)
*/
LPC18XX_CGU->xtal_osc_ctrl |= LPC18XX_CGU_XTAL_ENABLE;
#if CONFIG_LPC18XX_EXTOSC_RATE > 15000000
LPC18XX_CGU->xtal_osc_ctrl |= LPC18XX_CGU_XTAL_HF;
#else
LPC18XX_CGU->xtal_osc_ctrl &= ~LPC18XX_CGU_XTAL_HF;
#endif
LPC18XX_CGU->xtal_osc_ctrl &= ~LPC18XX_CGU_XTAL_ENABLE;
/*
* Wait for the external oscillator to stabilize
*/
cycle_delay(1000000);
/*
* PLL1 disabled while altering values
*/
LPC18XX_CGU->pll1_ctrl &= ~LPC18XX_CGU_PLL1CTRL_PD_MSK;
/*
* PLL1 clksrc = xtal
*/
LPC18XX_CGU->pll1_ctrl =
(LPC18XX_CGU->pll1_ctrl & ~LPC18XX_CGU_CLKSEL_MSK) |
LPC18XX_CGU_CLKSEL_XTAL | LPC18XX_CGU_AUTOBLOCK_MSK;
/*
* Configure PLL1 for desired output
*/
LPC18XX_CGU->pll1_ctrl =
(LPC18XX_CGU->pll1_ctrl &
~(LPC18XX_CGU_PLL1CTRL_FBSEL_MSK |
LPC18XX_CGU_PLL1CTRL_BYPASS_MSK |
LPC18XX_CGU_PLL1CTRL_DIRECT_MSK |
LPC18XX_CGU_PLL1CTRL_PSEL_MSK |
LPC18XX_CGU_PLL1CTRL_NSEL_MSK |
LPC18XX_CGU_PLL1CTRL_MSEL_MSK)) |
((CONFIG_LPC18XX_PLL1_M - 1) <<
LPC18XX_CGU_PLL1CTRL_MSEL_BITS) |
(0 << LPC18XX_CGU_PLL1CTRL_NSEL_BITS) |
(1 << LPC18XX_CGU_PLL1CTRL_PSEL_BITS) |
LPC18XX_CGU_PLL1CTRL_DIRECT_MSK |
LPC18XX_CGU_PLL1CTRL_FBSEL_MSK;
/*
* Now enable PLL1
*/
LPC18XX_CGU->pll1_ctrl &= ~LPC18XX_CGU_PLL1CTRL_PD_MSK;
/*
* Wait for PLL1 to acquire lock
*/
while (lock_count < MIN_LOCK_PERIOD_MS) {
if (!(LPC18XX_CGU->pll1_stat & LPC18XX_CGU_PLL1STAT_LOCK)) {
lock_count = 0;
} else {
lock_count++;
}
cycle_delay(5000);
}
/*
* Now safe to switch to PLL1 for M4 core clock
*/
LPC18XX_CGU->m4_clk =
(LPC18XX_CGU->m4_clk & ~LPC18XX_CGU_CLKSEL_MSK) |
LPC18XX_CGU_CLKSEL_PLL1 | LPC18XX_CGU_AUTOBLOCK_MSK;
/* Wait 1ms */
cycle_delay(60000);
/*
* Set-up clocks for UARTs
*/
#ifdef CONFIG_UART0_CLOCK_XTAL
LPC18XX_CGU->uart0_clk = LPC18XX_CGU_CLKSEL_XTAL |
LPC18XX_CGU_AUTOBLOCK_MSK;
#else
LPC18XX_CGU->uart0_clk = LPC18XX_CGU_CLKSEL_PLL1 |
LPC18XX_CGU_AUTOBLOCK_MSK;
#endif
LPC18XX_CGU->uart1_clk = LPC18XX_CGU_CLKSEL_PLL1 |
LPC18XX_CGU_AUTOBLOCK_MSK;
LPC18XX_CGU->uart2_clk = LPC18XX_CGU_CLKSEL_PLL1 |
LPC18XX_CGU_AUTOBLOCK_MSK;
LPC18XX_CGU->uart3_clk = LPC18XX_CGU_CLKSEL_PLL1 |
LPC18XX_CGU_AUTOBLOCK_MSK;
#if defined(CONFIG_LPC_SPI)
/*
* Set-up clocks for SPI
*/
LPC18XX_CGU->spifi_clk = LPC18XX_CGU_CLKSEL_PLL1 |
LPC18XX_CGU_AUTOBLOCK_MSK;
#endif
}
/*
* Set-up the external crystal oscillator, PLL1, CPU core clock and
* all necessary clocks for peripherals.
*/
static void clock_setup(void)
{
/*
* Configure and enable the external crystal oscillator
*/
#if CONFIG_LPC18XX_EXTOSC_RATE > 15000000
LPC18XX_CGU->xtal_osc_ctrl |= LPC18XX_CGU_XTAL_HF;
#else
LPC18XX_CGU->xtal_osc_ctrl &= ~LPC18XX_CGU_XTAL_HF;
#endif
LPC18XX_CGU->xtal_osc_ctrl &= ~LPC18XX_CGU_XTAL_ENABLE;
/*
* Wait for the external oscillator to stabilize
*/
cycle_delay(1000000);
/*
* Switch the M4 core clock to the 12MHz external oscillator
*/
LPC18XX_CGU->m4_clk =
(LPC18XX_CGU->m4_clk & ~LPC18XX_CGU_CLKSEL_MSK) |
LPC18XX_CGU_CLKSEL_XTAL | LPC18XX_CGU_AUTOBLOCK_MSK;
LPC18XX_CGU->pll1_ctrl =
(LPC18XX_CGU->pll1_ctrl & ~LPC18XX_CGU_CLKSEL_MSK) |
LPC18XX_CGU_CLKSEL_XTAL | LPC18XX_CGU_AUTOBLOCK_MSK;
/*
* Configure PLL1 for a 108MHz output, because we cannot set
* the maximum frequency right away.
*/
LPC18XX_CGU->pll1_ctrl =
(LPC18XX_CGU->pll1_ctrl &
~(LPC18XX_CGU_PLL1CTRL_FBSEL_MSK |
LPC18XX_CGU_PLL1CTRL_BYPASS_MSK |
LPC18XX_CGU_PLL1CTRL_DIRECT_MSK |
LPC18XX_CGU_PLL1CTRL_PSEL_MSK |
LPC18XX_CGU_PLL1CTRL_NSEL_MSK |
LPC18XX_CGU_PLL1CTRL_MSEL_MSK)) |
((LPC18XX_PLL1_M_INTERMEDIATE - 1) <<
LPC18XX_CGU_PLL1CTRL_MSEL_BITS) |
(0 << LPC18XX_CGU_PLL1CTRL_NSEL_BITS) |
(1 << LPC18XX_CGU_PLL1CTRL_PSEL_BITS) |
LPC18XX_CGU_PLL1CTRL_DIRECT_MSK |
LPC18XX_CGU_PLL1CTRL_FBSEL_MSK;
/*
* Make sure the PLL1 is enabled
*/
LPC18XX_CGU->pll1_ctrl &= ~LPC18XX_CGU_PLL1CTRL_PD_MSK;
/*
* Wait for PLL1 to acquire lock
*/
while (!(LPC18XX_CGU->pll1_stat & LPC18XX_CGU_PLL1STAT_LOCK));
/*
* Switch the MCU M4 core to PLL1
*/
LPC18XX_CGU->m4_clk =
(LPC18XX_CGU->m4_clk & ~LPC18XX_CGU_CLKSEL_MSK) |
LPC18XX_CGU_CLKSEL_PLL1 | LPC18XX_CGU_AUTOBLOCK_MSK;
/* Wait 1ms */
cycle_delay(60000);
/*
* Clear the PLL1 control register before switching to the maximum
* output frequency. The MCU hangs otherwise.
*/
LPC18XX_CGU->pll1_ctrl &=
~(LPC18XX_CGU_PLL1CTRL_FBSEL_MSK |
LPC18XX_CGU_PLL1CTRL_BYPASS_MSK |
LPC18XX_CGU_PLL1CTRL_DIRECT_MSK |
LPC18XX_CGU_PLL1CTRL_PSEL_MSK |
LPC18XX_CGU_PLL1CTRL_NSEL_MSK |
LPC18XX_CGU_PLL1CTRL_MSEL_MSK);
/*
* Configure PLL1 for the requested output frequency
*/
LPC18XX_CGU->pll1_ctrl |=
((CONFIG_LPC18XX_PLL1_M - 1) <<
LPC18XX_CGU_PLL1CTRL_MSEL_BITS) |
(0 << LPC18XX_CGU_PLL1CTRL_NSEL_BITS) |
(0 << LPC18XX_CGU_PLL1CTRL_PSEL_BITS) |
LPC18XX_CGU_PLL1CTRL_DIRECT_MSK |
LPC18XX_CGU_PLL1CTRL_FBSEL_MSK;
/*
* Wait for PLL1 to stabilize
*/
cycle_delay(1000000);
/*
* Set-up clocks for UARTs
*/
LPC18XX_CGU->uart0_clk = LPC18XX_CGU_CLKSEL_PLL1 |
LPC18XX_CGU_AUTOBLOCK_MSK;
LPC18XX_CGU->uart1_clk = LPC18XX_CGU_CLKSEL_PLL1 |
LPC18XX_CGU_AUTOBLOCK_MSK;
LPC18XX_CGU->uart2_clk = LPC18XX_CGU_CLKSEL_PLL1 |
LPC18XX_CGU_AUTOBLOCK_MSK;
LPC18XX_CGU->uart3_clk = LPC18XX_CGU_CLKSEL_PLL1 |
LPC18XX_CGU_AUTOBLOCK_MSK;
}
