//
// Fill in the details of a PCMCIA slot and initialize the device
//
void
cf_hwr_init(struct cf_slot *slot)
{
static int int_init = 0;
unsigned long new_state = *SA11X0_GPIO_PIN_LEVEL;
if (!int_init) {
int_init = 1;
#ifdef CYGPKG_KERNEL
// Set up interrupts
cyg_drv_interrupt_create(SA1110_CF_DETECT,
99, // Priority - what goes here?
(cyg_addrword_t) slot, // Data item passed to interrupt handler
(cyg_ISR_t *)cf_detect_isr,
(cyg_DSR_t *)cf_detect_dsr,
&cf_detect_interrupt_handle,
&cf_detect_interrupt);
cyg_drv_interrupt_attach(cf_detect_interrupt_handle);
cyg_drv_interrupt_configure(SA1110_CF_DETECT, true, true); // Detect either edge
cyg_drv_interrupt_acknowledge(SA1110_CF_DETECT);
cyg_drv_interrupt_unmask(SA1110_CF_DETECT);
cyg_drv_interrupt_create(SA1110_CF_IRQ,
99, // Priority - what goes here?
(cyg_addrword_t) slot, // Data item passed to interrupt handler
(cyg_ISR_t *)cf_irq_isr,
(cyg_DSR_t *)cf_irq_dsr,
&cf_irq_interrupt_handle,
&cf_irq_interrupt);
cyg_drv_interrupt_attach(cf_irq_interrupt_handle);
cyg_drv_interrupt_unmask(SA1110_CF_IRQ);
#endif
cyg_drv_interrupt_configure(SA1110_CF_IRQ, false, false); // Falling edge
cyg_drv_interrupt_acknowledge(SA1110_CF_IRQ);
}
slot->attr = (unsigned char *)0x38000000;
slot->attr_length = 0x200;
slot->io = (unsigned char *)0x30000000;
slot->io_length = 0x04000000;
slot->mem = (unsigned char *)0x3C000000;
slot->mem_length = 0x04000000;
slot->int_num = SA1110_CF_IRQ;
#ifdef CYG_HAL_STARTUP_ROM
// Disable CF bus & power (idle/off)
assabet_BCR(SA1110_BCR_CF_POWER |
SA1110_BCR_CF_RESET |
SA1110_BCR_CF_BUS,
SA1110_BCR_CF_POWER_OFF |
SA1110_BCR_CF_RESET_DISABLE |
SA1110_BCR_CF_BUS_OFF);
#endif
if ((new_state & SA1110_GPIO_CF_DETECT) == SA1110_GPIO_CF_PRESENT) {
if ((_assabet_BCR & SA1110_BCR_CF_POWER) == SA1110_BCR_CF_POWER_ON) {
// Assume that the ROM environment has turned the bus on
slot->state = CF_SLOT_STATE_Ready;
} else {
slot->state = CF_SLOT_STATE_Inserted;
}
} else {
slot->state = CF_SLOT_STATE_Empty;
}
}
// Function to initialize the device. Called at bootstrap time.
static bool
vrc437x_serial_init(struct cyg_devtab_entry *tab)
{
serial_channel *chan = (serial_channel *)tab->priv;
vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv;
static bool init = false;
#ifdef CYGDBG_IO_INIT
diag_printf("VRC437X SERIAL init '%s' - dev: %x\n", tab->name, vrc437x_chan->base);
#endif
(chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices
if (!init && chan->out_cbuf.len != 0) {
init = true;
// Note that the hardware is rather broken. The interrupt status needs to
// be read using only channel A
cyg_drv_interrupt_create(VRC437X_SCC_INT,
99,
(cyg_addrword_t)VRC437X_SCC_BASE+SCC_CHANNEL_A,
vrc437x_serial_ISR,
vrc437x_serial_DSR,
&vrc437x_serial_interrupt_handle,
&vrc437x_serial_interrupt);
cyg_drv_interrupt_attach(vrc437x_serial_interrupt_handle);
cyg_drv_interrupt_unmask(VRC437X_SCC_INT);
}
vrc437x_serial_config_port(chan, &chan->config, true);
return true;
}
static void
aeb_setup_timer1(cyg_uint32 period)
{
cyg_uint32 iocr;
// Set counter GATE input low (0) to halt counter while it's being setup
HAL_READ_UINT32(CYG_DEVICE_IOCR, iocr);
iocr = (iocr & ~IOCR_CT1G) | IOCR_CT1G_LOW;
HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr);
// Scale timer0 clock
HAL_WRITE_UINT32(CYG_DEVICE_CPM_CT1CCR, CT_X16);
// Initialize counter, mode 2 = rate generator
HAL_WRITE_UINT8(CYG_DEVICE_TIMER_CTL,
TIMER_CTL_TYPE_BIN|
TIMER_CTL_MODE_RG|
TIMER_CTL_RW_BOTH|
TIMER_CTL_SC_CTR1);
HAL_WRITE_UINT8(CYG_DEVICE_TIMER1, (period & 0xFF)); // LSB
HAL_WRITE_UINT8(CYG_DEVICE_TIMER1, ((period >> 8) & 0xFF)); // MSB
// Enable timer
iocr = (iocr & ~IOCR_CT1G) | IOCR_CT1G_HIGH;
HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr);
cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_TIMER1,
99, // Priority
0, // Data item passed to interrupt handler
aeb_timer1_isr,
0,
&timer1_interrupt_handle,
&timer1_interrupt);
cyg_drv_interrupt_attach(timer1_interrupt_handle);
cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_TIMER1);
}
// Serial I/O - high level interrupt handler (DSR)
static void
smdk2410_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
serial_channel *chan = (serial_channel *)data;
smdk2410_serial_info *smdk2410_chan = (smdk2410_serial_info *)chan->dev_priv;
CYG_ADDRWORD base = smdk2410_chan->base;
cyg_uint32 _intsubpnd, _status, _c;
cyg_uint32 _rxd_bit = (smdk2410_chan->bit_sub_rxd<<0), _txd_bit=(smdk2410_chan->bit_sub_rxd<<1);
HAL_READ_UINT32(SUBSRCPND, _intsubpnd);
// Empty Rx FIFO
if (_intsubpnd & _rxd_bit) {
HAL_READ_UINT32(base+OFS_UFSTAT, _status);
while((_status & 0x0f) != 0) {
HAL_READ_UINT8(base+OFS_URXH, _c);
(chan->callbacks->rcv_char)(chan, (unsigned char)_c);
HAL_READ_UINT32(base+OFS_UFSTAT, _status);
}
HAL_WRITE_UINT32(SUBSRCPND, _rxd_bit);
}
// Fill into Tx FIFO. xmt_char will mask the interrupt when it
// runs out of chars, so doing this in a loop is OK.
if (_intsubpnd & _txd_bit) {
(chan->callbacks->xmt_char)(chan);
HAL_WRITE_UINT32(SUBSRCPND, _txd_bit);
}
cyg_drv_interrupt_unmask(smdk2410_chan->int_num);
}
// Serial I/O - high level interrupt handler (DSR)
static void
aaed2000_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
serial_channel *chan = (serial_channel *)data;
aaed2000_serial_info *aaed2000_chan = (aaed2000_serial_info *)chan->dev_priv;
CYG_ADDRWORD base = aaed2000_chan->base;
cyg_uint32 _intres, _c;
HAL_READ_UINT32(base+AAEC_UART_INTRES, _intres);
_intres &= (AAEC_UART_INT_TIS | AAEC_UART_INT_RIS | AAEC_UART_INT_RTIS);
while (_intres) {
// Empty Rx FIFO
if (_intres & (AAEC_UART_INT_RIS|AAEC_UART_INT_RTIS)) {
HAL_READ_UINT32(base+AAEC_UART_DATA, _c);
(chan->callbacks->rcv_char)(chan, (unsigned char)_c);
}
// Fill into Tx FIFO. xmt_char will mask the interrupt when it
// runs out of chars, so doing this in a loop is OK.
if (_intres & AAEC_UART_INT_TIS) {
(chan->callbacks->xmt_char)(chan);
}
HAL_READ_UINT32(base+AAEC_UART_INTRES, _intres);
_intres &= (AAEC_UART_INT_TIS | AAEC_UART_INT_RIS | AAEC_UART_INT_RTIS);
}
cyg_drv_interrupt_unmask(aaed2000_chan->int_num);
}
static void phy_dsr(cyg_vector_t vector, cyg_ucount32 count,
cyg_addrword_t data)
{
cyg_uint32 status;
struct eth_drv_sc *sc = (struct eth_drv_sc *) data;
cyg_uint32 address =
((struct tsec_eth_info *) sc->driver_private)->phyAddress;
// os_printf("PHY DSR");
status = phy_read_register(address, MII_PHY_IRQ_REG);
if (status & (MII_PHY_IRQ_LINK_CHANGE| MII_PHY_IRQ_DUPLEX_CHANGE
| MII_PHY_IRQ_SPEED_CHANGE))
{
int esa_ok = 0;
(sc->funs->stop)(sc);
// Try to read the ethernet address of the transciever ...
#ifdef CYGPKG_REDBOOT
esa_ok = flash_get_config("tsec_esa", enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"tsec_esa", enaddr, CONFIG_ESA);
#endif
if (!esa_ok)
{
// Can't figure out ESA
os_printf("TSEC_ETH - Warning! ESA unknown\n");
memcpy(&enaddr, &_default_enaddr, sizeof(enaddr));
}
(sc->funs->start)(sc, (unsigned char *) enaddr, 1);
}
cyg_drv_interrupt_unmask(vector);
}
// Function to initialize the device. Called at bootstrap time.
static bool
edb7xxx_serial_init(struct cyg_devtab_entry *tab)
{
serial_channel *chan = (serial_channel *)tab->priv;
edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv;
#ifdef CYGDBG_IO_INIT
diag_printf("EDB7XXX SERIAL init - dev: %x.%d\n", edb7xxx_chan->control, edb7xxx_chan->tx_int_num);
#endif
(chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices
if (chan->out_cbuf.len != 0) {
cyg_drv_interrupt_create(edb7xxx_chan->tx_int_num,
99, // Priority - unused
(cyg_addrword_t)chan, // Data item passed to interrupt handler
edb7xxx_serial_tx_ISR,
edb7xxx_serial_tx_DSR,
&edb7xxx_chan->serial_tx_interrupt_handle,
&edb7xxx_chan->serial_tx_interrupt);
cyg_drv_interrupt_attach(edb7xxx_chan->serial_tx_interrupt_handle);
cyg_drv_interrupt_mask(edb7xxx_chan->tx_int_num);
edb7xxx_chan->tx_enabled = false;
}
if (chan->in_cbuf.len != 0) {
cyg_drv_interrupt_create(edb7xxx_chan->rx_int_num,
99, // Priority - unused
(cyg_addrword_t)chan, // Data item passed to interrupt handler
edb7xxx_serial_rx_ISR,
edb7xxx_serial_rx_DSR,
&edb7xxx_chan->serial_rx_interrupt_handle,
&edb7xxx_chan->serial_rx_interrupt);
cyg_drv_interrupt_attach(edb7xxx_chan->serial_rx_interrupt_handle);
cyg_drv_interrupt_unmask(edb7xxx_chan->rx_int_num);
}
edb7xxx_serial_config_port(chan, &chan->config, true);
return true;
}
// Serial I/O - high level interrupt handler (DSR)
static void zynq_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
serial_channel *chan = (serial_channel *)data;
zynq_serial_info *zynq_chan = (zynq_serial_info *)chan->dev_priv;
volatile cyg_uint32 isr;
cyg_uint32 status, temp;
unsigned char c;
HAL_READ_UINT32(zynq_chan->base + XUARTPS_CHNL_INT_STS, isr);
if (isr & XUARTPS_CHNL_INT_STS_TEMPTY)
(chan->callbacks->xmt_char)(chan);
if ((isr & XUARTPS_CHNL_INT_STS_RTRIG) || (isr & XUARTPS_CHNL_INT_STS_RTOUT)) // Data in the RxFiFo
{
HAL_READ_UINT32(zynq_chan->base + XUARTPS_CHANNEL_STS, status);
while( !(status & XUARTPS_CHANNEL_STS_REMPTY) )
{
HAL_READ_UINT32(zynq_chan->base + XUARTPS_TX_RX_FIFO, temp);
c = (unsigned char)(temp & 0xff);
(chan->callbacks->rcv_char)(chan, c);
HAL_READ_UINT32(zynq_chan->base + XUARTPS_CHANNEL_STS, status);
}
}
// clear
HAL_WRITE_UINT32(zynq_chan->base + XUARTPS_CHNL_INT_STS, isr);
cyg_drv_interrupt_unmask(zynq_chan->int_num);
}
void
kbd_init(void)
{
// Initialize environment, setup interrupt handler
cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_KBDINT,
99, // Priority - what goes here?
0, // Data item passed to interrupt handler
(cyg_ISR_t *)keyboard_isr,
(cyg_DSR_t *)keyboard_dsr,
&kbd_interrupt_handle,
&kbd_interrupt);
cyg_drv_interrupt_attach(kbd_interrupt_handle);
cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_KBDINT);
cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_KBDINT);
// Set up the mbox for keyboard data
cyg_mbox_create(&kbd_events_mbox_handle, &kbd_events_mbox);
// This semaphore is set when there is a keypress
cyg_semaphore_init(&kbd_sem, 0);
// Create a thread whose job it is to de-bounce the keyboard and
// actually process the input, turning it into a series of events
cyg_thread_create(10, // Priority - just a number
kbd_server, // entry
0, // initial parameter
"KBD_server", // Name
&kbd_server_stack[0], // Stack
STACK_SIZE, // Size
&kbd_server_thread_handle, // Handle
&kbd_server_thread_data // Thread data structure
);
cyg_thread_resume(kbd_server_thread_handle); // Start it
}
//==========================================================================
// This function is called from the generic ADC package to enable the
// channel in response to a CYG_IO_SET_CONFIG_ADC_ENABLE config operation.
// It should take any steps needed to start the channel generating samples
//==========================================================================
static void at91_adc_enable(cyg_adc_channel *chan)
{
at91_adc_info *info = chan->device->dev_priv;
// Enable the channel
HAL_WRITE_UINT32((info->adc_base + AT91_ADC_CHER), \
AT91_ADC_CHER_CHx(chan->channel));
//
// Unmask interrupt as soon as 1 channel is enable
//
if (!info->chan_mask)
{
cyg_drv_interrupt_unmask(info->timer_vector);
// Enable timer interrupt
HAL_WRITE_UINT32(info->tc_base+AT91_TC_IER, AT91_TC_IER_CPC);
// Enable the clock
HAL_WRITE_UINT32(info->tc_base+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);
// Start timer
HAL_WRITE_UINT32(info->tc_base+AT91_TC_CCR, AT91_TC_CCR_TRIG);
// Start ADC sampling
HAL_WRITE_UINT32((info->adc_base + AT91_ADC_CR), AT91_ADC_CR_START);
}
info->chan_mask |= AT91_ADC_CHER_CHx(chan->channel);
}
// Enable the transmitter on the device (nope, already in use by hal_diag)
static void
ebsa285_serial_start_xmit(serial_channel *chan)
{
ebsa285_serial_info *ebsa285_chan = (ebsa285_serial_info *)chan->dev_priv;
ebsa285_chan->tx_active = 1;
cyg_drv_interrupt_unmask(ebsa285_chan->tx.int_num);
}
void hal_clock_initialize(cyg_uint32 period)
{
cyg_uint32 tmod;
// Disable timer 0
HAL_READ_UINT32(E7T_TMOD, tmod);
tmod &= ~(E7T_TMOD_TE0);
HAL_WRITE_UINT32(E7T_TMOD, 0);
tmod &= ~(E7T_TMOD_TMD0 | E7T_TMOD_TCLR0);
tmod |= E7T_TMOD_TE0;
// Set counter
HAL_WRITE_UINT32(E7T_TDATA0, period);
// And enable timer
HAL_WRITE_UINT32(E7T_TMOD, tmod);
_period = period;
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_EXT0,
99, // Priority
0, // Data item passed to interrupt handler
e7t_abort_isr,
0,
&abort_interrupt_handle,
&abort_interrupt);
cyg_drv_interrupt_attach(abort_interrupt_handle);
cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_EXT0);
#endif
}
static void
mpc8xxx_scc_serial_DSR(serial_channel *chan)
{
mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv;
volatile struct scc_regs_8260 *ctl = (volatile struct scc_regs_8260 *)smc_chan->ctl;
volatile struct cp_bufdesc *txbd;
volatile struct cp_bufdesc *rxbd = smc_chan->rxbd;
volatile t_Smc_Pram *pram = (volatile t_Smc_Pram *)smc_chan->pram;
struct cp_bufdesc *rxlast;
int i, cache_state;
if (ctl->scce & SCCE_Tx) {
// Transmit interrupt
ctl->scce = SCCE_Tx; // Reset interrupt state;
txbd = smc_chan->tbase; // First buffer
while (true) {
if ((txbd->ctrl & (_BD_CTL_Ready|_BD_CTL_Int)) == _BD_CTL_Int) {
txbd->length = 0;
txbd->ctrl &= ~_BD_CTL_Int; // Reset interrupt bit
}
if (txbd->ctrl & _BD_CTL_Wrap) {
txbd = smc_chan->tbase;
break;
} else {
txbd++;
}
}
(chan->callbacks->xmt_char)(chan);
}
while (ctl->scce & SCCE_Rx) {
// Receive interrupt
ctl->scce = SCCE_Rx; // Reset interrupt state;
rxlast = (struct cp_bufdesc *) ((char *)IMM + pram->rbptr);
while (rxbd != rxlast) {
if ((rxbd->ctrl & _BD_CTL_Ready) == 0) {
for (i = 0; i < rxbd->length; i++) {
(chan->callbacks->rcv_char)(chan, rxbd->buffer[i]);
}
// Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
HAL_DCACHE_IS_ENABLED(cache_state);
if (cache_state) {
HAL_DCACHE_INVALIDATE(rxbd->buffer, smc_chan->rxsize); // Make sure no stale data
}
rxbd->length = 0;
rxbd->ctrl |= _BD_CTL_Ready;
}
if (rxbd->ctrl & _BD_CTL_Wrap) {
rxbd = smc_chan->rbase;
} else {
rxbd++;
}
}
smc_chan->rxbd = (struct cp_bufdesc *)rxbd;
}
if (ctl->scce & SCCE_Bsy) {
ctl->scce = SCCE_Bsy; // Reset interrupt state;
}
cyg_drv_interrupt_acknowledge(smc_chan->int_num);
cyg_drv_interrupt_unmask(smc_chan->int_num);
}
// Enable the transmitter (interrupt) on the device
static void
edb7xxx_serial_start_xmit(serial_channel *chan)
{
edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv;
edb7xxx_chan->tx_enabled = true;
cyg_drv_interrupt_unmask(edb7xxx_chan->tx_int_num);
}
__externC CYG_WORD32 cyg_hal_cpu_message_dsr(CYG_WORD32 vector, CYG_ADDRWORD data) {
struct smp_msg_t *m = &smp_msg[HAL_SMP_CPU_THIS()];
CYG_WORD32 reschedule;
#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE
CYG_WORD32 timeslice;
#endif
cyg_drv_interrupt_mask(vector);
HAL_SPINLOCK_SPIN(m->lock);
reschedule = m->reschedule;
#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE
timeslice = m->timeslice;
m->reschedule = m->timeslice = false;
#else
m->reschedule = false;
#endif
HAL_SPINLOCK_CLEAR(m->lock);
cyg_drv_interrupt_unmask(vector);
if (reschedule) {
cyg_scheduler_set_need_reschedule();
}
#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE
if (timeslice) {
cyg_scheduler_timeslice_cpu();
}
#endif
return 0;
}
// Function to initialize the device. Called at bootstrap time.
static bool
smdk2410_serial_init(struct cyg_devtab_entry *tab)
{
serial_channel *chan = (serial_channel *)tab->priv;
smdk2410_serial_info *smdk2410_chan = (smdk2410_serial_info *)chan->dev_priv;
cyg_uint32 _intsubm;
#ifdef CYGDBG_IO_INIT
diag_printf("SMDK2410 SERIAL init - dev: 0x%08x.%d\n",
smdk2410_chan->base, smdk2410_chan->int_num);
#endif
(chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices
if (chan->out_cbuf.len != 0) {
cyg_drv_interrupt_create(smdk2410_chan->int_num,
1, // Priority - unused
(cyg_addrword_t)chan, // Data item passed to interrupt handler
smdk2410_serial_ISR,
smdk2410_serial_DSR,
&smdk2410_chan->serial_interrupt_handle,
&smdk2410_chan->serial_interrupt);
cyg_drv_interrupt_attach(smdk2410_chan->serial_interrupt_handle);
cyg_drv_interrupt_unmask(smdk2410_chan->int_num);
HAL_READ_UINT32(INTSUBMSK, _intsubm);
_intsubm &= ~(smdk2410_chan->bit_sub_rxd<<0); // BIT_SUB_RXD
HAL_WRITE_UINT32(INTSUBMSK, _intsubm);
}
smdk2410_serial_config_port(chan, &chan->config, true);
return true;
}
bool altera_avalon_uart_init(struct cyg_devtab_entry *tab)
{
serial_channel *chan = (serial_channel *)tab->priv;
altera_avalon_uart_dev *uart_chan = (altera_avalon_uart_dev *)chan->dev_priv;
(chan->callbacks->serial_init)(chan);
/* enable interrupts at the device */
if (chan->out_cbuf.len != 0)
{
cyg_drv_interrupt_create(uart_chan->irq,
99, /* Priority - unused */
(cyg_addrword_t)chan, /* Data item passed to interrupt handler */
altera_avalon_uart_ISR,
altera_avalon_uart_DSR,
&uart_chan->serial_interrupt_handle,
&uart_chan->serial_interrupt);
cyg_drv_interrupt_attach(uart_chan->serial_interrupt_handle);
IOWR_ALTERA_AVALON_UART_CONTROL(uart_chan->base,
ALTERA_AVALON_UART_CONTROL_RTS_MSK |
ALTERA_AVALON_UART_CONTROL_RRDY_MSK |
ALTERA_AVALON_UART_CONTROL_DCTS_MSK);
cyg_drv_interrupt_unmask(uart_chan->irq);
}
return true;
}
// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
static bool emaclite_init(struct cyg_netdevtab_entry *dtp)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *)dtp->device_instance;
struct emaclite_info *qi = (struct emaclite_info *)sc->driver_private;
unsigned char _enaddr[6];
bool esa_ok;
/* Try to read the ethernet address of the transciever ... */
#if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
esa_ok = flash_get_config(qi->esa_key, _enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
qi->esa_key, _enaddr, CONFIG_ESA);
#endif
if (esa_ok) {
memcpy(qi->enaddr, _enaddr, sizeof(qi->enaddr));
} else {
/* No 'flash config' data available - use default */
diag_printf("Emaclite_ETH - Warning! Using default ESA for '%s'\n", dtp->name);
}
/* Initialize Xilinx driver - device id 0*/
if (XEmacLite_Initialize(&qi->dev, 0) != XST_SUCCESS) {
diag_printf("Emaclite_ETH - can't initialize\n");
return false;
}
if (XEmacLite_SelfTest(&qi->dev) != XST_SUCCESS) {
diag_printf("Emaclite_ETH - self test failed\n");
return false;
}
XEmacLite_SetMacAddress(&qi->dev, qi->enaddr);
XEmacLite_SetSendHandler(&qi->dev, sc, emaclite_TxEvent);
XEmacLite_SetRecvHandler(&qi->dev, sc, emaclite_RxEvent);
#ifdef CYGPKG_NET
/* Set up to handle interrupts */
cyg_drv_interrupt_create(qi->int_vector,
0, // Highest //CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data passed to ISR
(cyg_ISR_t *)emaclite_isr,
(cyg_DSR_t *)eth_drv_dsr,
&qi->emaclite_interrupt_handle,
&qi->emaclite_interrupt);
cyg_drv_interrupt_attach(qi->emaclite_interrupt_handle);
cyg_drv_interrupt_acknowledge(qi->int_vector);
cyg_drv_interrupt_unmask(qi->int_vector);
#endif
/* Operating mode */
_s3esk_dev = &qi->dev;
/* Initialize upper level driver for ecos */
(sc->funs->eth_drv->init)(sc, (unsigned char *)&qi->enaddr);
return true;
}
// Serial I/O - high level rx interrupt handler (DSR)
static void
e7t_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
serial_channel *chan = (serial_channel *)data;
e7t_serial_info *e7t_chan = (e7t_serial_info *)chan->dev_priv;
volatile struct serial_port *port = (volatile struct serial_port *)e7t_chan->base;
(chan->callbacks->rcv_char)(chan, port->REG_URXBUF);
cyg_drv_interrupt_unmask(e7t_chan->rx_int_num);
}
// Deliver function (ex-DSR) handles the ethernet [logical] processing
static void
quicc_eth_deliver(struct eth_drv_sc * sc)
{
quicc_eth_int(sc);
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
// Allow interrupts to happen again
cyg_drv_interrupt_unmask(QUICC_ETH_INT);
#endif
}
// Deliver function (ex-DSR) handles the ethernet [logical] processing
static void
quicc_eth_deliver(struct eth_drv_sc * sc)
{
quicc_eth_int(sc);
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
// Allow interrupts to happen again
cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_CPM_SCC1);
#endif
}
//------------------------------------------
// The high level transmit interrupt handler
//------------------------------------------
static void mpc555_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
serial_channel * chan = (serial_channel *)data;
mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv;
(chan->callbacks->xmt_char)(chan);
if(mpc555_chan->tx_interrupt_enable)
cyg_drv_interrupt_unmask(mpc555_chan->tx_interrupt_num);
}
//-------------------------------------
// Enable the transmitter on the device
//-------------------------------------
static void mpc555_serial_start_xmit(serial_channel * chan)
{
mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv;
mpc555_chan->tx_interrupt_enable = true;
cyg_drv_interrupt_unmask(mpc555_chan->tx_interrupt_num);
// No need to call xmt_char, this will generate an interrupt immediately.
}
// Initialize hardware (including startup)
void netxeth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
{
PNETX_ETH_PORT_INFO ptPortInfo = sc->driver_private;
cyg_uint32 uiPhyData;
cyg_uint32 ulPort = ptPortInfo->ulPort;
cyg_uint32 ulIdx;
cyg_uint32 ulFifoOffset = 8 * ulPort;
cyg_uint16* pusMAC = (cyg_uint16*)ptPortInfo->abMAC;
xc_reset(ptPortInfo->ulPort);
xc_load(ptPortInfo->ulPort,
ptPortInfo->pulRPECFirmware,
NULL,
ptPortInfo->pulxMACRPUFirmware,
ptPortInfo->pulxMACTPUFirmware);
// local mac config
ptPortInfo->pulRPECDram[REL_Adr_ETHMAC_TRAFFIC_CLASS_ARRANGEMENT / sizeof(cyg_uint32)] = (0x8 << SRT_ETHMAC_TRAFFIC_CLASS_ARRANGEMENT_VAL);
for(ulIdx = 1; ulIdx < (MAX_SEND_SLOTS + 1); ulIdx++)
{
ptPortInfo->atSendFrames[ulIdx - 1].ulSegment = ptPortInfo->ulPort;
ptPortInfo->atSendFrames[ulIdx - 1].ulFrameNr = ulIdx;
ptPortInfo->atSendFrames[ulIdx - 1].ulKey = 0;
ptPortInfo->atSendFrames[ulIdx - 1].fUsed = false;
}
for(ulIdx = MAX_SEND_SLOTS + 1; ulIdx < MAX_SLOTS; ulIdx++)
{
FIFO_POINTER tPtr = {0};
tPtr.tBf.uiSegment = ptPortInfo->ulPort;
tPtr.tBf.uiFrameNr = ulIdx;
s_ptFifoArea->aulPfifo[ulFifoOffset + EMPTY_PTR_FIFO] = tPtr.uiVal;
}
/* Enable all interrupt sources */
ptPortInfo->pulRPECDram[REL_Adr_ETHMAC_INTERRUPTS_ENABLE_IND_HI / sizeof(cyg_uint32)] = MSK_ETHMAC_INTERRUPTS_ENABLE_IND_HI_VAL;
ptPortInfo->pulRPECDram[REL_Adr_ETHMAC_INTERRUPTS_ENABLE_IND_LO / sizeof(cyg_uint32)] = MSK_ETHMAC_INTERRUPTS_ENABLE_IND_LO_VAL;
ptPortInfo->pulRPECDram[REL_Adr_ETHMAC_INTERRUPTS_ENABLE_CON_HI / sizeof(cyg_uint32)] = MSK_ETHMAC_INTERRUPTS_ENABLE_CON_HI_VAL;
ptPortInfo->pulRPECDram[REL_Adr_ETHMAC_INTERRUPTS_ENABLE_CON_LO / sizeof(cyg_uint32)] = MSK_ETHMAC_INTERRUPTS_ENABLE_CON_LO_VAL;
ptPortInfo->pulRPECDram[REL_Adr_ETHMAC_LOCAL_MAC_ADDRESS_HI / sizeof(cyg_uint32)] = pusMAC[2];
ptPortInfo->pulRPECDram[REL_Adr_ETHMAC_LOCAL_MAC_ADDRESS_LO / sizeof(cyg_uint32)] = (pusMAC[1] << 16) |
pusMAC[0];
xc_start(ptPortInfo->ulPort);
//Wakeup phy from powerdown
PhyMDIO(s_abPhyAddresses[ptPortInfo->ulPort], MDIO_READ, DRV_CB12_CONTROL, &uiPhyData);
uiPhyData = DRV_CB12_CONTROL_AUTO_NEG_ENABLE;
PhyMDIO(s_abPhyAddresses[ptPortInfo->ulPort], MDIO_WRITE, DRV_CB12_CONTROL, &uiPhyData);
cyg_drv_interrupt_unmask(ptPortInfo->ulInterrupt);
}
// Enable the transmitter on the device
static void
e7t_serial_start_xmit(serial_channel *chan)
{
e7t_serial_info *e7t_chan = (e7t_serial_info *)chan->dev_priv;
e7t_chan->tx_enabled = true;
(chan->callbacks->xmt_char)(chan);
if (e7t_chan->tx_enabled) {
cyg_drv_interrupt_unmask(e7t_chan->tx_int_num);
}
}
// Deliver function (ex-DSR) handles the ethernet [logical] processing
static void
fec_eth_deliver(struct eth_drv_sc * sc)
{
fec_eth_int(sc);
#ifdef _FEC_USE_INTS
// Allow interrupts to happen again
cyg_drv_interrupt_acknowledge(FEC_ETH_INT);
cyg_drv_interrupt_unmask(FEC_ETH_INT);
#endif
}
// Serial I/O - high level Tx interrupt handler (DSR)
static void
edb7xxx_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
serial_channel *chan = (serial_channel *)data;
edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv;
(chan->callbacks->xmt_char)(chan);
if (edb7xxx_chan->tx_enabled) {
cyg_drv_interrupt_unmask(edb7xxx_chan->tx_int_num);
}
}
static void
ebsa285_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
serial_channel *chan = (serial_channel *)data;
ebsa285_serial_info *ebsa285_chan = (ebsa285_serial_info *)chan->dev_priv;
if ((*SA110_UART_FLAG_REGISTER & SA110_TX_FIFO_STATUS_MASK) != SA110_TX_FIFO_BUSY) {
(chan->callbacks->xmt_char)(chan);
}
if ( ebsa285_chan->tx_active ) // it might be halted in callback above
cyg_drv_interrupt_unmask(ebsa285_chan->tx.int_num);
}
// Deliver function (ex-DSR) handles the ethernet [logical] processing
static void
fec_eth_deliver(struct eth_drv_sc * sc)
{
fec_eth_int(sc);
#ifdef CYGPKG_NET
// Clearing the event register acknowledges FCC2 interrupt ...
// cyg_drv_interrupt_acknowledge(FEC_ETH_INT);
cyg_drv_interrupt_unmask(FEC_ETH_INT);
#endif
}
// Serial I/O - high level Rx interrupt handler (DSR)
static void
edb7xxx_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
serial_channel *chan = (serial_channel *)data;
edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv;
volatile cyg_uint32 *datreg = (volatile cyg_uint32 *)edb7xxx_chan->data;
volatile cyg_uint32 *stat = (volatile cyg_uint32 *)edb7xxx_chan->stat;
while (!(*stat & SYSFLG1_URXFE1))
(chan->callbacks->rcv_char)(chan, *datreg);
cyg_drv_interrupt_unmask(edb7xxx_chan->rx_int_num);
}
