static void display_banner (void)
{
char *version = "AT91Bootstrap";
char *ver_num = " "AT91BOOTSTRAP_VERSION" ("COMPILE_TIME")";
dbgu_print("\n\r");
dbgu_print("\n\r");
dbgu_print(version);
dbgu_print(ver_num);
dbgu_print("\n\r");
dbgu_print("\n\r");
}
/*------------------------------------------------------------------------------*/
void hw_init(void)
{
unsigned int cp15;
/*
* Configure PIOs
*/
const struct pio_desc hw_pio[] = {
#ifdef CONFIG_DEBUG
{"RXD", AT91C_PIN_PA(21), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"TXD", AT91C_PIN_PA(22), 0, PIO_DEFAULT, PIO_PERIPH_A},
#endif
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Disable watchdog
*/
writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
/*
* At this stage the main oscillator is supposed to be enabled
* * PCK = MCK = MOSC
*/
/*
* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA
*/
pmc_cfg_plla(PLL_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* PCK = PLL = 2 * MCK
*/
pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* Switch MCK on PLLA output
*/
pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* Enable External Reset
*/
writel(AT91C_RSTC_KEY_UNLOCK
|| AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/*
* Configure CP15
*/
cp15 = get_cp15();
//cp15 |= I_CACHE;
set_cp15(cp15);
#ifdef CONFIG_SCLK
sclk_enable();
#endif
/*
* Configure the PIO controller to output PCK0
*/
pio_setup(hw_pio);
#ifdef CONFIG_DEBUG
/*
* Enable Debug messages on the DBGU
*/
dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
dbgu_print("Start AT91Bootstrap...\n\r");
#endif /* CONFIG_VERBOSE */
/*
* Configure the EBI Slave Slot Cycle to 64
*/
writel((readl((AT91C_MATRIX_SCFG4)) & ~0xFF) | 0x40, AT91C_MATRIX_SCFG4);
/*
* Initialize the matrix Slave 0 & Slave 4 (SRAM & EBI)
*/
writel(readl(AT91C_MATRIX_SCFG0) | AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR |
AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D, AT91C_MATRIX_SCFG0);
writel(readl(AT91C_MATRIX_SCFG4) | AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR |
AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D, AT91C_MATRIX_SCFG4);
#ifdef CONFIG_SDRAM
/*
* Initialize the matrix
*/
writel(readl(AT91C_CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC, AT91C_CCFG_EBICSA);
#ifdef MCK_100
/*
* Configure SDRAM Controller
*/
sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 | AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8, /* Control Register */
(MASTER_CLOCK * 7) / 1000000, /* Refresh Timer Register */
AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */
#else /* 133 MHz */
/*
* Configure SDRAM Controller
*/
sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_9 | AT91C_SDRAMC_TRP_3 | AT91C_SDRAMC_TRCD_3 | AT91C_SDRAMC_TRAS_6 | AT91C_SDRAMC_TXSR_10, /* Control Register */
(MASTER_CLOCK * 7) / 1000000, /* Refresh Timer Register */
AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */
#endif
#endif
}
/*----------------------------------------------------------------------------*/
void hw_init(void)
{
unsigned int cp15;
/*
* Configure PIOs
*/
const struct pio_desc hw_pio[] = {
#ifdef CONFIG_DEBUG
{"RXD", AT91C_PIN_PA(9), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"TXD", AT91C_PIN_PA(10), 0, PIO_DEFAULT, PIO_PERIPH_A},
#endif
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Disable watchdog
*/
writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
/*
* At this stage the main oscillator is supposed to be enabled
* * PCK = MCK = MOSC
*/
writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR);
/*
* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA
*/
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* PCK = PLLA/2 = 3 * MCK
*/
pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK, PLL_LOCK_TIMEOUT);
/*
* Switch MCK on PLLA output
*/
pmc_cfg_mck(BOARD_PRESCALER_PLLA, PLL_LOCK_TIMEOUT);
/*
* Enable External Reset
*/
writel(AT91C_RSTC_KEY_UNLOCK
|| AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/*
* Configure CP15
*/
cp15 = get_cp15();
cp15 |= I_CACHE;
set_cp15(cp15);
#ifdef CONFIG_SCLK
sclk_enable();
#endif
/*
* Configure the PIO controller
*/
writel((1 << AT91C_ID_PIOA_B), (PMC_PCER + AT91C_BASE_PMC));
pio_setup(hw_pio);
/*
* Enable Debug messages on the DBGU
*/
#ifdef CONFIG_DEBUG
dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
dbgu_print("Start AT91Bootstrap...\n\r");
#endif
#ifdef CONFIG_DDR2
/*
* Configure DDRAM Controller
*/
dbg_log(1, "Init DDR... ");
ddramc_hw_init();
dbg_log(1, "Done!\n\r");
#endif /* CONFIG_DDR2 */
}
int main(void)
{
struct image_info image;
char *media_str = NULL;
int ret;
char filename[FILENAME_BUF_LEN];
char of_filename[FILENAME_BUF_LEN];
memset(&image, 0, sizeof(image));
memset(filename, 0, FILENAME_BUF_LEN);
memset(of_filename, 0, FILENAME_BUF_LEN);
image.dest = (unsigned char *)JUMP_ADDR;
#ifdef CONFIG_OF_LIBFDT
image.of = 1;
image.of_dest = (unsigned char *)OF_ADDRESS;
#endif
#ifdef CONFIG_NANDFLASH
media_str = "NAND: ";
image.offset = IMG_ADDRESS;
image.length = IMG_SIZE;
#ifdef CONFIG_OF_LIBFDT
image.of_offset = OF_OFFSET;
image.of_length = OF_LENGTH;
#endif
#endif
#ifdef CONFIG_DATAFLASH
media_str = "SF: ";
image.offset = IMG_ADDRESS;
image.length = IMG_SIZE;
#ifdef CONFIG_OF_LIBFDT
image.of_offset = OF_OFFSET;
image.of_length = OF_LENGTH;
#endif
#endif
#ifdef CONFIG_SDCARD
media_str = "SD/MMC: ";
image.filename = filename;
strcpy(image.filename, OS_IMAGE_NAME);
#ifdef CONFIG_OF_LIBFDT
image.of_filename = of_filename;
strcpy(image.of_filename, OF_FILENAME);
#endif
#endif
#ifdef CONFIG_HW_INIT
hw_init();
#endif
display_banner();
#ifdef CONFIG_LOAD_ONE_WIRE
/* Load one wire informaion */
load_1wire_info();
#endif
init_loadfunction();
ret = (*load_image)(&image);
if (media_str)
dbgu_print(media_str);
if (ret == 0){
dbgu_print("Done to load image\n\r");
}
if (ret == -1) {
dbgu_print("Failed to load image\n\r");
while(1);
}
if (ret == -2) {
dbgu_print("Success to recovery\n\r");
while (1);
}
#ifdef CONFIG_SCLK
slowclk_switch_osc32();
#endif
return JUMP_ADDR;
}
/*----------------------------------------------------------------------------*/
void hw_init(void)
{
unsigned int cp15;
/*
* Configure PIOs
*/
const struct pio_desc hw_pio[] = {
#ifdef CONFIG_DEBUG
{"RXD", AT91C_PIN_PB(14), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"TXD", AT91C_PIN_PB(15), 0, PIO_DEFAULT, PIO_PERIPH_A},
#endif
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Disable watchdog
*/
writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
/*
* At this stage the main oscillator is supposed to be enabled
* * PCK = MCK = MOSC
*/
writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR);
/*
* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA
*/
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* PCK = PLLA/2 = 3 * MCK
*/
pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* Switch MCK on PLLA output
*/
pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* Configure PLLB
*/
pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* Enable External Reset
*/
writel(AT91C_RSTC_KEY_UNLOCK
|| AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/*
* Configure CP15
*/
cp15 = get_cp15();
//cp15 |= I_CACHE;
set_cp15(cp15);
/*
* Enable External Reset
*/
writel(AT91C_RSTC_KEY_UNLOCK
|| AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/*
* Configure the PIO controller
*/
pio_setup(hw_pio);
/*
* Configure the EBI Slave Slot Cycle to 64
*/
writel((readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40,
(AT91C_BASE_MATRIX + MATRIX_SCFG3));
#ifdef CONFIG_DEBUG
/*
* Enable Debug messages on the DBGU
*/
dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
dbgu_print("Start AT91Bootstrap...\n\r");
#endif /* CONFIG_DEBUG */
#ifdef CONFIG_SDRAM
/*
* Initialize the matrix (memory voltage = 3.3)
*/
writel((readl(AT91C_BASE_CCFG + CCFG_EBICSA)) | AT91C_EBI_CS1A_SDRAMC |
(1 << 16), AT91C_BASE_CCFG + CCFG_EBICSA);
/*
* Configure SDRAM Controller
*/
sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_3 | AT91C_SDRAMC_TRC_9 | AT91C_SDRAMC_TRP_3 | AT91C_SDRAMC_TRCD_3 | AT91C_SDRAMC_TRAS_6 | AT91C_SDRAMC_TXSR_10, /* Control Register */
(MASTER_CLOCK * 7) / 1000000, /* Refresh Timer Register */
AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */
#endif /* CONFIG_SDRAM */
}
