int decon_reg_is_win_enabled(int idx) { if (decon_read(WINCON(idx)) & WINCONx_ENWIN) return 1; return 0; }
irqreturn_t decon_int_irq_handler(int irq, void *dev_data) { struct decon_device *decon = dev_data; u32 irq_sts_reg; ktime_t timestamp; u32 fifo_level; timestamp = ktime_get(); spin_lock(&decon->slock); if ((decon->state == DECON_STATE_OFF) || (decon->state == DECON_STATE_LPD)) { goto irq_end; } irq_sts_reg = decon_read(decon->id, VIDINTCON1); if (irq_sts_reg & VIDINTCON1_INT_FRAME) { /* VSYNC interrupt, accept it */ decon_write_mask(decon->id, VIDINTCON1, ~0, VIDINTCON1_INT_FRAME); decon->vsync_info.timestamp = timestamp; wake_up_interruptible_all(&decon->vsync_info.wait); } if (irq_sts_reg & VIDINTCON1_INT_FIFO) { /* TODO: false underrun check only for EVT0. This will be removed in EVT1 */ fifo_level = FRAMEFIFO_FIFO0_VALID_SIZE_GET(decon_read(decon->id, FRAMEFIFO_REG7)); decon->underrun_stat.fifo_level = fifo_level; decon->underrun_stat.prev_overlap_cnt = decon->prev_overlap_cnt; decon->underrun_stat.cur_overlap_cnt = decon->cur_overlap_cnt; decon->underrun_stat.chmap = decon_read(0, WINCHMAP0); decon->underrun_stat.aclk = decon->res.aclk->rate; decon->underrun_stat.mif_pll = decon->res.mif_pll->rate; decon_int_get_enabled_win(decon); decon_oneshot_underrun_log(decon); decon_write_mask(decon->id, VIDINTCON1, ~0, VIDINTCON1_INT_FIFO); /* TODO: underrun function */ /* s3c_fb_log_fifo_underflow_locked(decon, timestamp); */ } if (irq_sts_reg & VIDINTCON1_INT_I80) { decon_write_mask(decon->id, VIDINTCON1, ~0, VIDINTCON1_INT_I80); } irq_end: spin_unlock(&decon->slock); return IRQ_HANDLED; }
u32 decon_reg_get_stop_status(void) { u32 val; val = decon_read(VIDCON0); if (val & VIDCON0_DECON_STOP_STATUS) return 1; return 0; }
static void decon_int_get_enabled_win(struct decon_device *decon) { int i; decon->underrun_stat.used_windows = 0; for (i = 0; i < decon->pdata->max_win; ++i) if (decon_read(decon->id, WINCON(i)) & WINCON_ENWIN) set_bit(i * 4, &decon->underrun_stat.used_windows); }
irqreturn_t decon_ext_dsi_irq_handler(int irq, void *dev_data) { struct decon_device *decon = dev_data; ktime_t timestamp = ktime_get(); u32 irq_sts_reg; u32 wb_irq_sts_reg; spin_lock(&decon->slock); irq_sts_reg = decon_read(decon->id, VIDINTCON1); wb_irq_sts_reg = decon_read(decon->id, VIDINTCON3); if (irq_sts_reg & VIDINTCON1_INT_FRAME) { /* VSYNC interrupt, accept it */ decon_write_mask(decon->id, VIDINTCON1, ~0, VIDINTCON1_INT_FRAME); decon->vsync_info.timestamp = timestamp; wake_up_interruptible_all(&decon->vsync_info.wait); } if (irq_sts_reg & VIDINTCON1_INT_FIFO) { decon_err("DECON-ext FIFO underrun\n"); decon_write_mask(decon->id, VIDINTCON1, ~0, VIDINTCON1_INT_FIFO); } if (irq_sts_reg & VIDINTCON1_INT_I80) { decon_write_mask(decon->id, VIDINTCON1, ~0, VIDINTCON1_INT_I80); wake_up_interruptible_all(&decon->wait_frmdone); } #if 0 if (wb_irq_sts_reg & VIDINTCON3_WB_FRAME_DONE) { decon_dbg("write-back frame done\n"); DISP_SS_EVENT_LOG(DISP_EVT_WB_FRAME_DONE, &decon->sd, ktime_set(0, 0)); decon_write_mask(decon->id, VIDINTCON3, ~0, VIDINTCON3_WB_FRAME_DONE); atomic_set(&decon->wb_done, STATE_DONE); wake_up_interruptible_all(&decon->wait_frmdone); decon_reg_per_frame_off(decon->id); decon_reg_update_standalone(decon->id); decon_reg_wb_swtrigger(decon->id); decon_reg_wait_stop_status_timeout(decon->id, 20 * 1000); } #endif spin_unlock(&decon->slock); return IRQ_HANDLED; }
/* wait until shadow update is finished */ int decon_reg_wait_for_update_timeout(unsigned long timeout) { unsigned long delay_time = 100; unsigned long cnt = timeout / delay_time; while ((decon_read(DECON_UPDATE) & DECON_UPDATE_STANDALONE_F) && cnt--) udelay(delay_time); if (!cnt) { decon_err("timeout of updating decon registers\n"); return -EBUSY; } return 0; }
u32 decon_reg_get_vstatus(void) { return decon_read(VIDCON1) & VIDCON1_VSTATUS_MASK; }
u32 decon_reg_get_linecnt(void) { return VIDCON1_LINECNT_GET(decon_read(VIDCON1)); }